{
{ CML$CPU_FAILURE_DATA
{
{
{ PURPOSE:
{    This statistic records the failure data captured by the system
{ following corrected or uncorrected CPU errors.
{
{ FREQUENCY: Each time DFT enters data into the maintenance
{            register buffers following each failure occurrence.
{
{ CONTENT:
{    The descriptive-data portion of this statistic contains:
{
{    '<mf>.<element>*<product id>*<serial number>*<symptom>'
{
{      where <mf> is the identification of the mainframe in the form
{        $SYSTEM_mmmm_ssss.  Where 'mmmm' is the model number of
{        Central Processor zero (CP0) and 'ssss' is the serial
{        number of that processor.
{
{      where <element> is the name CP0 for processor zero,
{        CP1 for processor one etc.
{
{      where <product id> is the model number from the processor's
{        element identification register.
{
{      where <serial number> is the serial number from the
{        processor's element identification register.
{
{      where <symptom> is the symptom/action statement provided
{        by the system. The text of the possible symptom statements
{        is identical in content to the uppercase text described
{        under counter value 2 below.
{
{    The counter-value portion of this statistic contains:
{
{    1. Operating System (OS) action code as described in section
{       4.2 of the DFT/OS Interface Specification. (DCS # ARH6853)
{
{    2. This word contains a 12-bit DFT analysis code followed by
{       an 8-bit sequence number stored in bits 44-63 of the word.
{       The sequence number indicates the sequential order in which
{       a series of statistics occurred, and ranges from 0-255(10).
{       Dedicated Fault Tolerance (DFT) analysis code is described
{       in section 4.4 of the DFT/OS Interface Specification. The
{       failure data should be analyzed in the order in which the
{       following codes are presented. (It should also be noted
{       that if bit 12 of the 12-bit hexadecimal DFT analysis code
{       is set, the error has occurred more than one time but is
{       being reported only once; e.g. code 203 will become A03.)
{
{       201 DEADSTART ERROR LOG PROCESSOR ERROR.
{       208 FATAL CPU HALT.
{       20B FATAL CPU RECOVERY ERROR (990 PROCESSOR ONLY).
{       20D FATAL CPU UNCORRECTED ERROR
{       21A FATAL CPU HALT CLASS 2.
{       207 UNREPAIRED ERROR (990 PROCESSOR ONLY).
{       204 UNCORRECTED PROCESSOR ERROR.
{       21B RETRY CONVERTED TO UNCORRECTED.
{       219 FORCED UNCORRECTED ERROR.
{       206 REPAIRED ERROR (990 PROCESSOR ONLY).
{       203 CORRECTED PROCESSOR ERROR.
{       20C CORRECTED PROCESSOR ERROR WITH CACHE RELOAD.
{       21C RETRY EXHAUSTED.
{       205 RETRY IN PROGRESS (990 PROCESSOR ONLY).
{       21D HOURLY RETRY THRESHOLD EXHAUSTED.
{
{     The content of words 3-63 is model dependent based upon
{     the DFT error analysis code. Packets of five words, each
{     consisting of a header word followed by the contents of four
{     maintenance registers are stored sequentially. The header
{     word consists of 4 16-bit maintenance register addresses
{     stored from left to right that specify which register
{     contents are stored in the following four words. Sections
{     4.5.9 (Code 3201), 4.5.6 (Codes 3208 and 3204), 4.5.5 (Codes
{     2203 and 0205) and 4.1.17 (Codes 3207 and 2206) of the
{     DFT/OS Interface Specification define the maintenance
{     registers and the order in which their contents are stored
{     for CPU errors.
{
  CONST
    cml$cpu_failure_data = cmc$min_ecc + 1000;

*copyc cmc$condition_limits
