{
{ CML$DVS_USAGE_DATA
{
{
{ PURPOSE:
{    The purpose of this statistic is to record usage of the
{ Diagnostic Virtual System Utility (DVS). Information recorded
{ by this statistic is used by maintenance personnel to assist
{ with location and isolation of system and mainframe faults.
{
{ FREQUENCY:
{    This statistic is emitted each time the DVS system is
{ initiated. DVS records the number of tests initiated, the
{ duration of their execution, and total number of failures that
{ have occurred. The counter-value portion of the statistic
{ records total pass and error counts for each of the tests that
{ can be executed. By convention, bit 0 (left-most bit) of a
{ counter-word indicates presence or absence of information in
{ the remainder of the word. A pass-count and error-count
{ counter-word with bit 0 set indicates that the corresponding
{ test was not initiated.
{
{ CONTENT:
{    The descriptive-data portion of this statistic contains:
{
{    '<mf>.<element>*<number_of_tests_initiated>*<execution_duration>..
{       *<number_of_tests_failed>'
{
{      where <mf> is the identification of the mainframe in the form
{        $SYSTEM_mmmm_ssss.  Where 'mmmm' is the model number of
{        Central Processor zero (CP0), e.g. 0990, and 'ssss' is the
{        serial number of that processor, e.g. 0104.
{
{      where <element> is the name DVS_TESTS_CP0 or DVS_TESTS_CP1.
{
{      where <number_of_tests_initiated> is a string representing
{        the decimal number of tests initiated by DVS during DVS's
{        duration of execution.
{
{      where <execution_duration> is a string representing the
{        decimal number of hours, minutes and seconds that DVS
{        was active.
{
{      where <number_of_tests_failed> is a string representing
{        the decimal number of tests of the total initiated that
{        detected errors. The counter-value portion of the
{        statistic identifies the specific tests that failed
{        and the number of errors detected.
{
{    The counter-value portion of the statistic contains:
{
{   1. RCT1 (Random Command Test 1) Total Passes Completed.
{   2. RCT1 (Random Command Test 1) Total Errors Detected.
{   3. RCT2 (Random Command Test 2) Total Passes Completed.
{   4. RCT2 (Random Command Test 2) Total Errors Detected.
{   5. FCT3 (Fixed Command Test 3) Total Passes Completed.
{   6. FCT3 (Fixed Command Test 3) Total Errors Detected.
{   7. SNGL (Single Precision Floating Point Test)
{              Total Passes Completed.
{   8. SNGL (Single Precision Floating Point Test)
{              Total Errors Detected.
{   9. DUBL (Double Precision Floating Point Test)
{              Total Passes Completed.
{  10. DUBL (Double Precision Floating Point Test)
{              Total Errors Detected.
{  11. BRCH (Floating Point Branch Test)
{              Total Passes Completed.
{  12. BRCH (Floating Point Branch Test)
{              Total Errors Detected.
{  13. FINT (Full Word Integer Test)
{              Total Passes Completed.
{  14. FINT (Full Word Integer Test)
{              Total Errors Detected.
{  15. HINT (Half Word Integer Test)
{              Total Passes Completed.
{  16. HINT (Half Word Integer Test)
{              Total Errors Detected.
{  17. FIMM (Full Word Immediate Test)
{              Total Passes Completed.
{  18. FIMM (Full Word Immediate Test)
{              Total Errors Detected.
{  19. HIMM (Half Word Immediate Test)
{              Total Passes Completed.
{  20. HIMM (Half Word Immediate Test)
{              Total Errors Detected.
{  21. NUMR (BDP Numeric Test)
{              Total Passes Completed.
{  22. NUMR (BDP Numeric Test)
{              Total Errors Detected.
{  23. BIMM (BDP Immediate Test)
{              Total Passes Completed.
{  24. BIMM (BDP Immediate Test)
{              Total Errors Detected.
{  25. RFST (Random Fast Slow Test)
{              Total Passes Completed.
{  26. RFST (Random Fast Slow Test)
{              Total Errors Detected.
{  27. DBUG (Debug Hardware Test)
{              Total Passes Completed.
{  28. DBUG (Debug Hardware Test)
{              Total Errors Detected.
{  29. TASE (Address Specification Error Test)
{              Total Passes Completed.
{  30. TASE (Address Specification Error Test)
{              Total Errors Detected.
{  31. TIVE (Instruction Specification Error Test)
{              Total Passes Completed.
{  32. TIVE (Instruction Specification Error Test)
{              Total Errors Detected.
{  33. BYTE (BDP Byte Test)
{              Total Passes Completed.
{  34. BYTE (BDP Byte Test)
{              Total Errors Detected.
{  35. EDIT (BDP Edit Test)
{              Total Passes Completed.
{  36. EDIT (BDP Edit Test)
{              Total Errors Detected.
{  37. VINT (Vector Integer Test)
{              Total Passes Completed.
{  38. VINT (Vector Integer Test)
{              Total Errors Detected.
{  39. VCMP (Vector Compare Test)
{              Total Passes Completed.
{  40. VCMP (Vector Compare Test)
{              Total Errors Detected.
{  41. VGTH (Vector Gather/Scatter Test)
{              Total Passes Completed.
{  42. VGTH (Vector Gather/Scatter Test)
{              Total Errors Detected.
{  43. VFLT (Vector Floating Point Test)
{              Total Passes Completed.
{  44. VFLT (Vector Floating Point Test)
{              Total Errors Detected.
{  45. KYPT (Keypoint Hardware Test)
{              Total Passes Completed.
{  46. KYPT (Keypoint Hardware Test)
{              Total Errors Detected.
{  47. DISK (Disk Test)
{              Total Passes Completed.
{  48. DISK (Disk Test)
{              Total Errors Detected.
{  49. TAPE (Tape Test)
{              Total Passes Completed.
{  50. TAPE (Tape Test)
{              Total Errors Detected.
{  51. CMEM (Central Memory and Disk Paging Test)
{              Total Passes Completed.
{  52. CMEM (Central Memory and Disk Paging Test)
{              Total Errors Detected.
{  53. PPCT (PP Instruction and Conflict Test)
{              Total Passes Completed.
{  54. PPCT (PP Instruction and Conflict Test)
{              Total Errors Detected.
{  55. VGSI (Vector Gather/Scatter Indexed Test)
{              Total Passes Completed.
{  56. VGSI (Vector Gather/Scatter Indexed Test)
{              Total Errors Detected.
{  57. VTRI (Vector Triad Test)
{              Total Passes Completed.
{  58. VTRI (Vector Triad Test)
{              Total Errors Detected.

  CONST
    cml$dvs_usage_data = cmc$min_ecc + 1900;

*copyc cmc$condition_limits
