{
{
{   CML$ICA_LAST_RESET_INFORMATION
{
{   PURPOSE :
{     This log message contains information on the last ICA reset.
{   If multiple resets occur before this message is delivered to the
{   PP, this message will only contain information concerning the first
{   reset.
{
{   FREQUENCY :
{      Following a successful load of the ICA.
{
{   CONTENT :
{      The descriptive-data portion of this statistic contains :
{
{      '<mf>.<iou>.<pp>.<channel>.<element>*<symptom>'
{
{      where <mf> is the identification of the mainframe in the form
{        $SYSTEM_mmmm_ssss.  Where 'mmmm' is the model number of
{        Central Processor zero (CP0),  e.g. 0990, and 'ssss' is the
{        serial number of that processor, e. g. 0104.
{
{      where <iou> is the string 'IOUn' where n is 0 or 1.  This
{        identifies the IOU associated with the channel over which
{        the statistic was reported.
{
{      where <pp> is the string 'PPn' or 'CPPn' where 'n' is the decimal
{        representation of the physical PP number used to process
{        the failing request. The C prefix is used to indicate that
{        the PP is a concurrent PP.
{
{      where <channel> is  the string 'CHn' or 'CCHn' ,
{        where 'n' is the decimal representation of the channel.
{        The C prefix is used to indicate that the channel is
{        a concurrent channel.
{
{      where <element> is the element name of the ICA.
{
{      where <symptom> is the symptom action statement provided
{        by the ICA:
{
{           'Last Reset Information'
{
{      The counter-value portion of this statistic contains :
{
{      1.   IOU number/Logical PP number
{           Bits 46 .. 51 = IOU number
{           bit  57       = 1 if concurrent pp
{           Bits 58 .. 63 = logical PP number
{      2.   IOU number/Channel Number of Controller
{           bits 00 .. 15 = channel error status if concurrent pp
{           Bits 46 .. 51 = IOU number
{           bit  57       = 1 if concurrent pp
{           Bits 58 .. 63 = Channel Number of Controller
{      3.   S/W Reset Reason Code
{
{         This  code represents the software reason that resulted in a
{         reset (if applicable).  All of these errors are captured  by
{         the controlware.
{
{         ICA-1  ICA-2
{         -----  -----
{           0      0   -  Non-SW reset reason (nothing saved in first 22 counters)
{           1      1   -  Deadman Timeout
{           2      2   -  Bus Error from CPU
{           3      3   -  Address Error from CPU
{           4      4   -  Illegal Instruction Error
{           5      5   -  Zero Divide
{           6     N/A  -  Double-bit Parity Error
{           7      7   -  Unrecoverable DMA Error
{           8      8   -  Unrecoverable Ethernet Error
{           9      9   -  Reset Function
{          10     N/A  -  Byte Write
{          11     11   -  General S/W Error
{          12     12   -  Transceiver Power Failure
{          N/A    13   -  Parity Error
{
{         Note  that Reason Code 6 can be from an ethernet controller,
{         DMA  controller,  or  CPU  memory  access.    The   "address
{         accessed" field will have to be the guide here.  The program
{         counter will only be helpful on a CPU double-bit error.
{
{      4.  MC68000 Status Register
{
{         This is the 16-bit status register value at the time of  the
{         interrupt  that  resulted  in  the  reset.  This register is
{         defined in the Motorola 68000 User's Manual.
{
{      5.  MC68000 Register State
{
{         This group of counters (17 counters) contains  all  the  ICA
{         processor's  registers  at  the  time  of the interrupt that
{         resulted in the reset.  They are  listed  in  the  following
{         order :
{
{           - 32-bit Program Counter
{           - 8 32-bit Data Registers D0 - D7
{           - 8 32-bit Address Registers A0 - A7
{
{         A6  will  always  point  to  the  beginning  of the register
{         storage area of the failure management table in  memory.   It
{         is not used elsewhere in the program.
{
{      22. Address Being Accessed
{
{         This is the 32-bit address being accessed at the time of the
{         interrupt.  This value may not always be applicable in which
{         case it will be 0.
{
{      23.  Diagnostic Status Table (DST) -- Reset Code
{
{           1 - Power On
{           2 - PP Master Clear
{           3 - Deadman Timeout
{           4 - Master Clear Switch
{           5 - Reset Function from PP
{           6 - MC68010 Reset Instruction
{
{           If multiple resets occurred since this message was last
{           sent, this counter represents the first reset that occurred.
{
{      24.  DST -- # of Resets since this message was last sent.
{
{      25.  DST -- Failure Code
{
{           0100(16) - Deadman Timer doesn't time out.
{           0200(16) - The address capture registers won't load
{                      properly.
{           0300(16) - Single-bit error(s) occurred while testing
{                      D/SRAM.
{           0400(16) - Transient multibit error(s) occurred during
{                      nondestructive D/SRAM testing.
{           0500(16) - Single-bit error(s) occurred during EEPROM
{                      checksum test.  EEPROM should be rewritten
{                      be ICA software.
{           0600(16) - A channel parity error was detected on a
{                      function.
{           0700(16) - A channel parity error was detected on a PP
{                      output operation.
{           0800(16) - A channel active timeout occurred during the
{                      CHANNEL ACTIVE TIMEOUT CHECK.
{
{      26.  DST -- # of Occurrences of this failure since this message
{           was last sent.
{
{      27.  DST -- Failure Code (As Above)
{
{      28.  DST -- # of Occurrences
{
{      29. - 40.  Failure Code /# of Occurrences Pairs
{
{      Counters  25  - 40 are optional; they will only be used if
{      the diagnostics encountered any of the errors listed during
{      their processing.   The counters not used will not be sent.

    CONST
       cml$ica_last_reset_information = cmc$min_ecc + 7103;


*copyc cmc$condition_limits
