{
{ CML$IVB_FAILURE_DATA
{
{
{ PURPOSE:
{    The purpose of this statistic is to record failure data
{    captured by NOS/VE when accessing the IVB.
{
{ FREQUENCY: At occurrence of failure.
{
{ CONTENT:
{    The  descriptive-data portion of this statistic contains:
{
{    '<mf>.<iou>.<pp>.<channel>.<element>*<severity>*<symptom>'
{
{      where <mf> is the identification of the mainframe in the form
{        $SYSTEM_mmmm_ssss.  Where 'mmmm' is the model number of
{        Central Processor zero (CP0), e.g. 0990, and 'ssss' is the
{        serial number of that processor, e.g. 0104.
{
{      where  <iou>  is  the  string  'IOUn' where n is 0 or 1.
{        This identifies the IOU associated with the channel over
{        which the failure was reported.
{
{      where <pp> is the string 'PPn' or 'CPPn' where 'n' is the decimal
{        representation of the physical PP number used to process
{        the failing request. The C prefix is used to indicate that
{        the PP is an I4 concurrent PP.
{
{      where <channel> is  the string 'CHn' or 'CCHn' ,
{        where 'n' is the decimal representation of the channel.
{        The C prefix is used to indicate that the channel is
{        an I4 concurrent channel.
{
{      where <element> is the element name of the IVB being
{        accessed when the failure occurred.
{
{      where <severity> is the string 'UF' for unrecovered, 'RF' for
{        recovered, 'IF' for intermediate failure log-entry, and 'IM'
{        for informative messages.
{
{        The PP reports failure data and diagnostic results  as  an
{        intermediate  failure  log-entry  prior  to retrying an i/o
{        request.  This is due to the fact that retry attempts are
{        not done immediatly but alternately with other I/O queued.
{        An intermediate failure    log-entry   will   provide   the
{        first-failure data captured by the PP  during  the  initial
{        attempt  at  the  request  or  during  a subsequent request
{        retry.
{
{        For  all failures the counter values contain
{        the failure data corresponding  to  the first  unsuccessful
{        try of the i/o request.
{
{      where <symptom> is the symptom/action statement  provided  by
{        the system.
{
{
{    The absence or presence of information in a counter word is
{    determined by the same convention used by other peripheral
{    statistics.  That is if bit 0, (left-most bit) of a counter word,
{    is not set the counter contains a bonafide value.
{
{    The counter-value portion of this statistic contains:
{
{    1.  IOU number/Logical PP number
{        Bits 46 .. 51 = IOU number
{        bit  57       = 1 if concurrent pp
{        Bits 58 .. 63 = logical PP number
{    2.  IOU number/Channel Number of Controller
{        bits 00 .. 15 = channel error status if concurrent pp
{        Bits 46 .. 51 = IOU number
{        bit  55       = 1 if I4 concurrent channel port A
{        bit  56       = 1 if I4 concurrent channel port B
{        bit  57       = 1 if concurrent pp
{        Bits 58 .. 63 = Channel Number of Controller
{    3.  Reserved for future use
{    4.  Log-entry Class
{        0 - Recovered Failure Report
{        1 - Unrecovered Failure Report
{        2 - Intermediate Failure Report
{        3 - Informative Message
{    5.  Failure Symptom Code (tells what the system thinks is wrong)
{
{         1  - FUNCTION   TIMEOUT  ERROR:  This  error  indicates  that  a
{              function timeout has occured.
{
{         2  - CHANNEL EMPTY: This error indicates that  the  IPI  channel
{              did not force the channel full when it was activated.
{
{         3  - PERIOD COUNTER PARITY: This is bit 51 of  the  IPI  channel
{              error register.
{
{         4  - UPPER  ICI  PARITY: This is bit 57 of the IPI channel error
{              register and indicates that a parity error has occurred  on
{              the  most  significant  byte of the channel between the IPI
{              chip and the PP.
{
{         5  - LOWER ICI PARITY: This is bit 58 of the IPI  channel  error
{              register  and  indicates a parity error has occurred on the
{              least significant byte of the channel between the IPI  chip
{              and the PP.
{
{         6  - IOU ERROR: This error indicates that the channel error flag
{              is set and none of  the  bits  in  the  IPI  channel  error
{              register or I4 IPI DMA error register are set.
{
{         7  - INCOMPLETE  TRANSFER:  This  error  indicates that the PP's
{              word count was nonzero after an I/O operation.
{
{         8  - CHANNEL NOT EMPTY: This error indicates  that  the  the  I4
{              channel  did  not  go  empty  after the output of parameter
{              words.
{
{         9  - CENTRAL MEMORY ERROR: This indicates that bit 50 or bit  51
{              of  the  I4  IPI  DMA  error  register  is  set and that an
{              uncorrected or reject  error  response  was  received  from
{              central memory.
{
{         10 - INVALID  CM RESPONSE CODE: This is bit 52 of the I4 IPI DMA
{              error register and indicates the response code from central
{              memory decoded into an illegal value.
{
{         11 - CM RESPONSE CODE PARITY ERROR: This is bit 53 of the I4 IPI
{              DMA error register and indicates  that  the  response  code
{              from central memory had a parity error.
{
{         12 - CMI  READ  DATA  PARITY ERROR: This is bit 54 of the I4 IPI
{              DMA error register and indicates that  the  central  memory
{              interface logic has detected a read data parity error.
{
{         13 - JY  DATA  ERROR:  This  is  bit  59 of the I4 IPI DMA error
{              register and indicates that the JY  board  has  detected  a
{              data parity error.
{
{         14 - BAS  PARITY  ERROR:  This is bit 60 of the I4 IPI DMA error
{              register and indicates that the LX  board  has  detected  a
{              parity error on data received from the barrel and  slot  of
{              the PP.
{
{         15 - LZ  ERROR:  This is bit 61 of the I4 IPI DMA error register
{              and indicates that the LZ board has detected an error.
{
{         16 - JY ERROR: This is bit 62 of the I4 IPI DMA  error  register
{              and indicates that the JY board has detected an error.
{
{         17 - LX  ERROR:  This is bit 63 of the I4 IPI DMA error register
{              and indicates that the LX board has detected an error.
{
{         20 - CANT SELECT: This error indicates that The  SLAVE  IN  line
{              was not set after the PP sent the select code to the IVB.
{
{         21 - BIT  SIGNIFICANT  RESPONSE ERROR: This error indicates that
{              the bit significant response which is in bits 56-63 of  the
{              IPI channel status register is incorrect.
{
{         22 - NO SYNC IN: This error indicates that During a bus  control
{              sequence SYNC IN did not set.
{
{         23 - SYNC  IN  DID  NOT DROP: This error indicates that During a
{              bus control sequence SYNC IN did not drop.
{
{         24 - IPI SEQUENCE ERROR: This is bit 59 of the IPI channel error
{              register  and  indicates  an  illegal  sequence  of control
{              signals has occurred on the IPI interface.
{
{         25 - UPPER IPI CHANNEL PARITY: This is bit 60 of the IPI channel
{              error  register  and  indicates  that  the  IPI channel has
{              detected a parity error on bus A of the IPI interface.
{
{         26 - LOWER IPI CHANNEL PARITY: This is bit 61 of the IPI channel
{              error  register  and  indicates  that  the  IPI channel has
{              detected a parity error on bus B of the IPI interface.
{
{         27 - SLAVE IN NOT SET:  This  error  indicates  that  during  an
{              ending  status  sequence  or  a  request  transfer settings
{              sequence SLAVE IN did not set.
{
{         28 - SLAVE IN DID NOT DROP: This error indicates that  During  a
{              deselect  sequence  or a command transfer sequence SLAVE IN
{              did not drop.
{
{         29 - CHANNEL ERROR: This error indicates that the channel  error
{              flag was set after reading the IPI or DMA registers.
{
{         30 - CHANNEL STAYED ACTIVE: This error indicates that  following
{              an information exchange the IVB did not drop SLAVE IN.  The
{              IVB drops SLAVE IN when the last word has been  transferred
{              or  if no words have been transferred for its timeout limit
{              of about 26 milliseconds.
{
{         31 - BUFFER COUNTER PARITY: This is bit 48 of  the  IPI  channel
{              error register.
{
{         32 - SYNC  COUNTER  PARITY:  This  is  bit 50 of the IPI channel
{              error register.
{
{         33 - LOST DATA:  This  is  bit  56  of  the  IPI  channel  error
{              register.   It indicates that the IVB ended a data transfer
{              and the IPI channel's buffer is not empty.
{
{         34 - BUS PARITY: This is bit 58 of ending status  received  from
{              the IVB.  It indicates that the IVB detected a parity error
{              on the IPI interface.
{
{         35 - COMMAND REJECT: This is reported in bits  60-63  of  ending
{              status  received from the IVB.  If a value of 2, 3, 6, or 8
{              is in these bits, the IVB has rejected the command sent  by
{              the PP.
{
{         36 - SYNC  OUT NOT EQ SYNC IN: This is reported in bits 60-63 of
{              ending status received from the IVB.  If these bits have  a
{              value  of 9, the IVB's SYNC OUT count and its SYNC IN count
{              were not equal when the transfer ended.
{
{         37 - BUS B ACK INCORRECT: This error indicates that during a bus
{              control sequence bus B received from the IVB was nonzero.
{
{         39 - ENDING STATUS WRONG: This error  is  reported  if  bit  56,
{              indicating  successful,  was  not set in ending status from
{              the IVB.
{
{         40 - IVB AVAILABLE: This error indicates  that  the  IVB  has
{              gone from not ready to ready.
{
{         41 - IVB  RESET:  This  error  indicates the IVB has switched to
{              reset state and  will  be  unavailable  for  an  indefinate
{              period of time.
{
{         42 - RESET FREQUENCY THRESHOLD: The IVB reset frequency threshold
{              was reached and the IVB has been downed.
{
{         100 - FORCED ERROR DID NOT OCCUR: This error indicates that  the
{               PP  forced  an  error during diagnostics but the error did
{               not occur.
{
{         200 - INVALID IPI READ RESPONSE: This error  indicates  that  an
{               invalid   read   response   was  received  from  the  IVB.
{
{         201 - INVALID IPI PARAMETER LENGTH: This error indicates that  a
{               parameter  was  received from the IVB for which the length
{               field was invalid.
{
{         202 - SEQUENCE  NUMBER  ERROR:  This  error  indicates  that   a
{               response  was  received  from  the  IVB which contained an
{               invalid sequence number.
{
{         203 - STATUS  MISMATCH:  This  error  indicates  that  the  host
{               indicated to the IVB that  an  operation  failed  but  the
{               status   returned   from  the  IVB  indicated  successful
{               completion.
{
{         205 - INVALID IPI RESPONSE OPCODE: This error indicates that  an
{               invalid operation  code was received with an IVB response.
{
{         206 - Invalid IPI response length: This error indicates that the
{               length  field  of  an IPI response was invalid.
{
{         207 - INVALID READ RESPONSE PARAMETER: This error indicates that
{               an  invalid  parameter  was received with an IPI response.
{
{         221 - INVALID DIAGNOSTIC RESPONSE: This error indicates that  an
{               invalid  diagnostic  response  was read.
{
{         229 - MAX CCPDU SIZE EXCEEDED: This error indicates that a ccpdu
{               was   received   which  exceeded  the  maximum  pdu  size.
{
{         230 - BUFFER REQUIRMENTS EXCEEDED: This error indicates that the
{               PP  does  not  support the maximum ccpdu size supported by
{               the IVB.
{
{         300 - RMA NOT ON WORD BOUNDARY: This error  indicates  a  system
{               error has occured.  A real memory address which must start
{               on a word boundary does not.
{
{         301 - CCPDU HEADER ERROR: This error  indicates  a  system error
{               has occured. A CCPDU header is not the correct size.
{
{         302 - INVALID UNIT REQUEST: This error  indicates  that  the  PP
{               received   an  unsupported  unit  request  from  the  CPU.
{
{         303 - WRITE REQUEST LENGTH ERROR: This error  indicates  that  a
{               write  request  received  from  the  CPU  was  of  invalid
{               length.
{
{         320 - IVB PROTOCOL NEGOTIATION FAILED: This error indicates that
{               the PP does not support the IPI or CC protocol proposed by
{               the IVB.
{
{         321 - INVALID  PP  COMMAND:  This  error  indicates  that the PP
{               received an unsupported command from the  CPU.
{
{         322 - UNEXPECTED CPU ACK: This error indicates that the CPU sent
{               an unexpected syncronization response to the PP.
{
{         323 - UNABLE TO CLEAR CHANNEL LOCK: This error indicates that  a
{               system  error  has  occured.   The  channel lock cannot be
{               cleared by the PP.
{
{         324 - INVALID BUFFER POOL DESCRIPTOR: This error indicates  that
{               a system error has occured. The buffer pool descriptors
{               are corrupted.
{
{         325 - MAXIMUM CCPDU SIZE REQUESTED ON SUSPEND LINK:  This error
{               indicates  that the maximum ccpdu size specified in the
{               suspend link request exceeds the maximum size supported.
{
{         350 - INDETERMINATE: This error indicates that an error has been
{               reported which can not be decoded to one of the preceding
{               errors.
{
{    6. Request Retry Count - The number of times the PP driver
{       retried the i/o request. (0..3)
{
{    7. Last Function - The last function sent from the PP to IVB.
{       (0 .. 0ffff(16))
{
{    8. Last -1 Function - The last -1 function sent from the PP to IVB.
{       (0 .. 0ffff(16))
{
{    9. Last -2 Function - The last -2 function sent from the PP to IVB.
{       (0 .. 0ffff(16))
{
{    10. Last -3 Function - The last -3 function sent from the PP to IVB.
{        (0 .. 0ffff(16))
{
{    11. Last -4 Function - The last -4 function sent from the PP to IVB.
{        (0 .. 0ffff(16))
{
{    12. Last -5 Function - The last -5 function sent from the PP to IVB.
{        (0 .. 0ffff(16))
{
{    13. Last -6 Function - The last -6 function sent from the PP to IVB.
{        (0 .. 0ffff(16))
{
{    14. Last -7 Function - The last -7 function sent from the PP to IVB.
{        (0 .. 0ffff(16))
{
{    15. Master Status - Last master status sent to the IVB.
{        (0 .. 0ffff(16))
{
{    16. Slave Status - Last slave status sent to the PP.
{        (0 .. 0ffff(16))
{
{    17. Operation Code - Operation code of the response in error
{        or the PP/UNIT command in error.
{        (0 .. 0ffff(16))
{
{    18. Parameter Id - Parameter identifier in error.
{        (0 .. 0ffff(16))
{
{    19. Expected Sequence Number - The  sequence number expected
{        with the failing response.
{        (0 .. 0ffff(16))
{
{    20. Actual Sequence Number - The  sequence number received
{        with the failing response.
{        (0 .. 0ffff(16))
{
{    21. Supported Protocol - Defines the IPI and CC protocol supported
{        by the host.  (0 .. 0ffff(16) defined as IICC) were II  indicates the
{        IPI protocol and CC indicates the Channel Connection protocol.
{        ie the value 0203(16) would define a IPI protocal of 2 and a
{        Channel Connection protocal of 3.
{
{    22. IVB Proposed Pprotocol - Defines the IPI and CC protocol supported
{        by the IVB.  (0 .. 0ffff(16) defined as IICC) were II  indicates the
{        IPI protocol and CC indicates the Channel Connection protocol.
{        ie the value 0203(16) would define a IPI protocal of 2 and a
{        Channel Connection protocal of 3.
{
{    23. REQUIRED BUFFERS - Number of buffers required by the PP to read
{        the maximum sized ccpdu.
{
{    24. MAXIMUM BUFFERS - Maximum number of buffers the PP is designed
{        to aquire for one ccpdu.
{
{    25. Length - This could be the length of a response or ccpdu
{        depending on error type.
{
{    26. IPI Status register - (0 .. 0FFFF(16)).
{
{    27. IPI Error register - (0 .. 0FFFF(16)).
{
{    28. DMA Error register - (0 .. 0FFFF(16)).
{
{    29. DMA Status register - (0 .. 0FFFF(16)).
{
{    30. DMA Control register - (0 .. 0FFFF(16)).
{
{    31. Expected Length - If error is incomplete transfer this counter
{        defines the expected length of the transfer. (0 .. 0FFFF(16).
{
{    32. Actual Length - If error is incomplete transfer this counter
{        defines the actual length of the transfer. (0 .. 0FFFF(16).
{
{    33. MAXIMUM CCPDU LENGTH - This counter indicates the maximum ccdpu
{        size supported by the IVB. This counter is included only with
{        the device available message.
{
{    34 - 38. RESERVED FOR PP - These words are reserved for debugging
{             purposes and should not be reported by HPA.

  CONST
    cml$ivb_failure_data = cmc$min_ecc + 7004;

*copyc cmc$condition_limits

