{
{ CML$MEMORY_FAILURE_DATA
{
{
{ PURPOSE:
{    This statistic records the failure data captured by the system
{ following corrected or uncorrected central memory errors.
{
{ FREQUENCY: Each time DFT enters data into the maintenance
{            register buffers following each failure occurrence.
{
{ CONTENT:
{    The descriptive-data portion of this statistic contains:
{
{    '<mf>.<element>*<product id>*<serial number>*<symptom>'
{
{      where <mf> is the identification of the mainframe in the form
{        $SYSTEM_mmmm_ssss.  Where 'mmmm' is the model number of
{        Central Processor zero (CP0) and 'ssss' is the serial number
{        of that processor.
{
{      where <element> is the name CENTRAL_MEMORY.
{
{      where <product id> is the model number from the memory
{        element's identification register.
{
{      where <serial number> is the serial number from the
{        memory element's identification register.
{
{      where <symptom> is the symptom/action statement provided
{        by the system. The text of the possible symptom statements
{        is identical in content to the uppercase text described
{        under counter value 2 below.
{
{    The counter-value portion of this statistic contains:
{
{    1. Operating System (OS) action code as described in section
{       4.2 of the DFT/OS Interface Specification.(DCS # ARH6853)
{
{    2. This word contains a 12-bit DFT analysis code followed by
{       an 8-bit sequence number stored in bits 44-63 of the word.
{       The sequence number indicates the sequential order in which
{       a series of statistics occurred, and ranges from 0-255(10).
{       Dedicated Fault Tolerance (DFT) analysis code is described
{       in section 4.4 of the DFT/OS Interface Specification. The
{       failure data should be analyzed in the order in which the
{       following codes are presented. (It should also be noted
{       that if bit 12 of the 12-bit hexadecimal DFT analysis code
{       is set, the error has occurred more than one time but is
{       being reported only once; e.g. code 103 will become 903.)
{
{       101 DEADSTART ERROR LOG MEMORY ERROR.
{       105 MULTIPLE ODD BIT MEMORY ERROR.
{       104 UNCORRECTED MEMORY ERROR.
{       103 CORRECTED MEMORY ERROR.
{       108 UNCORRECTED MEMORY BOARD LEVEL ERROR.
{       109 UNCORRECTED CENTRAL MEMORY INTERFACE ERROR.
{
{     The content of words 3-63 is model dependent based upon
{     the DFT error analysis code. Packets of 5 words, each
{     consisting of a header word followed by the contents of 4
{     maintenance registers are stored sequentially. The header
{     word consists of 4 16-bit maintenance register addresses
{     stored from left to right that specify which register
{     contents are stored in the following four words. Sections
{     4.5.8 (Code 3101), 4.5.4 (Code 3104) and 4.5.3 (Code 2103)
{     of the DFT/OS Interface  Specification define the mainte-
{     nance registers and the order in which their contents are
{     stored for central memory errors. (No maintenance register
{     contents are stored for code 3105).
{
   CONST
     cml$memory_failure_data = cmc$min_ecc + 1001;

*copyc cmc$condition_limits
