          IDENT  DFT0,70B
          CIPPU  J
          MEMSEL 16
          BASE   MIXED
          TITLE  CTM$DFT 930 CLASS (DFT0).
          COMMENT *SMD* LVL=11
          COMMENT COPYRIGHT CONTROL DATA SYSTEMS INC. 1992
 DFT      SPACE  4,10
***       DFT - DEDICATED FAULT TOLERANCE.
*         B. R. HANSON.      82/06/21. (PRECURSOR KNOWN AS SMU)
*         G. J. FALCONER.    85/08/05. (DFT V1.0)
*         G. J. FALCONER.    86/02/27. (DFT V2.0)
 DFT      SPACE  4,10
***       DFT PERFORMS:
*
*         1) CAPTURING THE CONTENT OF MAINFRAME MAINTENANCE REGISTERS
*         FOR ERROR LOGGING, AND CLEARING HARDWARE ELEMENT ERRORS.
*
*         2) THE ACTUAL SEQUENCE OF STEPS TO DEADSTART THE SYSTEM, UNDER
*         THE DIRECTION OF *VPB* MODE OF *SCI*.
*
*         3) PROVIDING EXTERNALIZATIONS OF *2AP* FUNCTIONS TO NOS/VE.
 CONTROL  SPACE  4,10
**        ASSEMBLY PARAMETERS.


 PRGM     SET    2           SET *OVERLAY* MACRO TO *DFT* NAMES
*STEP$    SET    0           ASSEMBLE *STEP* CODE IF SYMBOL DEFINED

          LIST   X
*COPY     CTP$DFT_RELEASE_HISTORY
*COPY     CTH$DEDICATED_FAULT_TOLERANCE
          LIST   *
 COMMON   SPACE  4,10
**        COMMON DECKS.


*COPYC DSI$PP_MACROS
*COPYC DSI$MAINTENANCE_REGISTER_MACROS
*COPYC CTI$COMPASS_OS_LEVELS
*COPYC CTC$DFT_MACROS
*COPYC CTC$DFT_DIRECT_CELLS

          LIST   X
*COPYC CTI$CONSOLE_PACKET_DEFINITIONS
*COPYC CTI$DFT_ANALYSIS_CODES
*COPY DSC$PP_MR_AND_TPM_CONSTANTS
*COPY CTC$DFT_CONSTANTS
*COPY CTC$DFT_ACTION_NO_OVERFLOW
*COPY DSA$HARDWARE_TABLE_DEFINITIONS
*COPY DSA$VE_REQUESTS_TO_DFT
          LIST   *
*COPY DSI$PP_INSTRUCTION_MNEMONICS
          LIST   X
*COPY CTC$EI_CONTROL_BLOCK
          LIST   *
 MAIN     SPACE  4,10
**        START DEFINITION OF THE MAIN LOOP OF DFT.
*
*         S0/S0E WILL REQUIRE PACKET CODE, EICB UPDATE, AND
*         RELOCATION ROUTINES.

*COPYC CTP$DFT_MAIN_LOOP
*COPYC CTP$DFT_MAIN_LOOP_930
*COPYC CTP$DFT_MAIN_LOOP_PACKETS
*COPYC CTP$DFT_MAIN_LOOP_UPDATE_TIME

**        END OF DFT MAIN LOOP DEFINITIONS.

*COPYC CTC$DFT_GLOBAL_DATA
 TOUB     CON    TOBPS0      *2AP* OUTPUT BUFFER ADJUSTED FOR LINKAGE BYTES
 TINB     CON    TOIPS0      *2AP* INPUT BUFFER
 MPSR     CON    S0PMPS      *MPS* REGISTER NUMBER
 JPSR     CON    S0PJPS      *JPS* REGISTER NUMBER
 CSAR     CON    S0PCSA      *CSA* REGISTER NUMBER

*         MISCELLANEOUS S0/S0E-SPECIFIC GLOBAL LOCATIONS.

 CLST2    CON    0           FLAG DENOTING TWO IOU CLUSTERS  (1 = PRESENT)
 PMEI     CON    0           PAGE MAP ELEMENT INDEX
 S0EFLG   CON    0           SET NONZERO IF S0E MAINFRAME

*         GLOBAL LOCATIONS USED BY *AME* OVERLAY TO ANALYZE MEMORY ERRORS.

 BDER     CON    0           BOARD ERROR FOUND
 BKER     CON    0           BANK ERROR FOUND FLAG
 BKNO     CON    0           BANK NUMBER WITH AN ERROR
 BNKI     CON    0           BANK INDEX
 BRDI     CON    0           BOARD INDEX
 DEGR     CON    0           MEMORY DEGRADATION OFFSET (0 = NO DEGRADE)
 MEER     CON    0           FLAG INDICATING ANY MEMORY ERROR FOUND
 NBNK     CON    4           NUMBER OF BANKS (DEFAULT = 4)
 NBRDS    CON    0           NUMBER OF MEMORY BOARDS INSTALLED
 SBNK     CON    0           STARTING BANK TO SEARCH FROM (DEFAULT = 0)

*         GLOBAL LOCATIONS USED BY *APE* OVERLAY TO ANALYZE PROCESSOR ERRORS.

 CSA0     CON    0           SLOT 0 CONTROL STORE ADDRESS
 CSA1     CON    0           SLOT 1 CONTROL STORE ADDRESS
 CSA2     CON    0           SLOT 2 CONTROL STORE ADDRESS
 DUETRAP  CON    0           *DUE* TRAP FLAG
 PUEL     BSS    2*4         CPU REGISTER 0#880/0#881 CONTENTS
 PFCL     BSS    2*4         CPU REGISTER 0#890/0#891 CONTENTS
 RETRYC   CON    0           RETRY COUNTER
 RETRYL   CON    0           RETRY LIMIT

*         GLOBAL LOCATIONS USED BY FAULT SYMPTOM CODE GENERATION ROUTINES.

 BITN     BSS    1           MOST SIGNIFICANT ERROR BIT FOUND IN *REGN*
 BUS0     BSS    1           NONZERO IF BIT 39 SET IN REGISTER 90 - 94
 BUS2     BSS    1           NONZERO IF BIT 39 SET IN REGISTER A0 - A4
 REGC     BSS    1           NUMBER OF REGISTERS WITH MEANINGFUL ERROR BITS
 REGN     BSS    1           FIRST REGISTER WITH MEANINGFUL ERROR BIT
*COPYC CTP$DFT_RESIDENT_COMMON
 ECM      SPACE  4,10
**        ECM - EXECUTE CIP MODULE.
*
*         ENTRY  (L2AP) = 1, IF *2AP* LOAD REQUIRED.
*                       = 0, IF *2AP* ALREADY LOADED.
*
*         EXIT   RETURNS TO LOCATION *RCMRTN*.
*
*         USES   EI, T1, CM - CM+3, W0 - W3, *CALB*, *RDATA*.
*
*         CALLS  IIB, LOV, LSR, SPB, *TOEP*.
*
*         MACROS FINDCM, READMR, WRITMR.
*
*         NOTE   *2AP* REQUIRES THE OS BOUNDS REGISTER AND THE MEMORY
*         BOUNDS REGISTER TO BE SET UP PRIOR TO *2AP* UPDATING ITSELF
*         IN MEMORY.  MEMORY BOUNDS WILL BE DISABLED AND DFT IN OS BOUNDS
*         IS SET TO UPPER PP.



 ECM      SUBR               ENTRY/EXIT
          RJM    TIM         UPDATE TIMING OF EVENTS

*         FOR S0/S0E MAINFRAMES, *2AP* NEEDS TO BE LOADED ONLY ON FIRST CALL
*         OR AFTER AN MRT UPDATE HAS OCCURRED.

          LDM    L2AP        CHECK IF *2AP* LOAD REQUIRED
          ZJN    ECM0.2      IF NO LOAD REQUIRED
          LDN    0
          STM    L2AP
          FINDCM 2AP         FIND CIP MODULE
          CRDL   W0
          STDL   T1
          SODL   W3          DELETE HEADER WORD
          LDDL   T1
          ADC    RR+1
          CRML   TOAPS0,W3   LOAD *2AP*
 ECM0.2   LDM    UMEM        UPDATE *2AP* IN MEMORY FLAG
          ZJN    ECM1        IF NO UPDATE

*         SET OS BOUNDS AND DISABLE MEMORY BOUNDS, IF NECESSARY, BEFORE
*         CALLING *2AP* SINCE IT WILL OVERLAY THE SECONDARY ROUTINES OVERLAY.

          LDN    DSCM+2
          RJM    IIB
          CRDL   CM          GET CIP POINTER
          LRD    CM+1
          RJM    SPB         SET PP BOUNDS
          RJM    DBC         DISABLE MEMORY BOUNDS CHECKING
 ECM1     LDC    CALB        LOAD CALL BLOCK ADDRESS
          RJM    TOEPS0      CALL *2AP* TO PROCESS FUNCTION
          LDN    0
          STD    EI

*         CALL *2AP* TO UPDATE CIP IMAGE IF NECESSARY.

          LDM    UMEM        UPDATE *2AP* IN MEMORY FLAG
          ZJN    ECM4        IF NO UPDATE
          LDN    27          FUNCTION TO UPDATE *2AP* IN CENTRAL MEMORY
          STM    CALB
          LDC    CALB
          RJM    TOEPS0      RE-CALL *2AP* TO PROCESS FUNCTION
          LDN    0
          STD    EI

*         REENABLE MEMORY BOUNDS CHECKING IF DISABLED FOR *2AP* CALL.

 ECM4     LDM    UMEM        CHECK NEED TO REENABLE MEMORY BOUNDS
          ZJN    ECM6        IF MEMORY BOUNDS WERE NOT DISABLED
          RJM    EBC         ENABLE BOUNDS CHECKING
 ECM6     RJM    TIM         UPDATE TIMING OF EVENTS
          LJM    ECMX        RETURN
 COMMON   SPACE  4,10
**        COMMON DECKS.


*COPY DSI$FIND_CIP_MODULE
*COPY DSI$GET_HARDWARE_ELEMENT
*COPYC CTP$MR_PROTOCOL_PREPROCESS
*COPYC CTP$MR_RETRY_OPERATION_FOR_DFT
*COPYC CTP$MR_PROTOCOL_PROCESS
*COPYC CTP$MR_PROTOCOL_POSTPROCESS_930
*COPY DSI$PP_UTILITY_SUBROUTINES
          TITLE  S0/S0E-SPECIFIC PRESET.
          USE    PRESET
          QUAL   PRESET
*COPYC CTP$DFT_PRESET
*COPYC CTP$DFT_PRESET_NON_DUAL_I4
 SPO      SPACE  4,10
**        SPO - SETUP MEMORY PORT OFFSET.
*
*         NOTE   THIS ROUTINE PERFORMS NO OPERATION ON A 930 SYSTEM.


 SPO      SUBR               ENTRY/EXIT
          UJN    SPOX        RETURN
*COPY CTP$DFT_RETURN_ERROR_CODE
          USE    *
          QUAL   *

          OVERFLOW  10000    CHECK FOR OVERFLOW
          OVERLAY  (RESIDENT PART II),10000
          QUAL   *


*         CAUTION - CAUTION - CAUTION - CAUTION
*
*         DUE TO THE WAY THE CALL MECHANISM WORKS IT CAN ONLY SUPPORT A 12 BIT
*         ADDRESS ON A CALL. DO NOT PUT ANY *ROUTINES* IN THE RESIDENT II AREA WHICH
*         ON THE S0 STARTS AT 10000.
*
*         CAUTION - CAUTION - CAUTION - CAUTION




 CMP      SPACE  4,10
**        CMP - CHECK MEMORY PORT.
*
*         ENTRY  (RDATA) = MEMORY *EC* REGISTER.
*                (HBUF) = PROCESSOR INFORMATION.
*
*         EXIT   (A) = 0, IF CPU MEMORY PORT ENABLED.
*                    > 0, IF CPU MEMORY PORT DISABLED.


 CMP      SUBR               ENTRY/EXIT
          LDM    S0EFLG      CHECK CPU TYPE
          NJN    CMP11       IF S0E

*         CHECK S0 PROCESSOR ENABLE/DISABLE STATUS.

          LDM    RDATA       CHECK MEMORY PORT 2/3 DISABLE STATUS
          LPN    0#18
          UJN    CMPX        RETURN

*         CHECK S0E PROCESSOR ENABLE/DISABLE STATUS.

 CMP11    LDM    HBUF+CPRPC  DETERMINE CPU NUMBER
          LPN    1
          STD    T1
          READMR RDATA,S0PMC,S0PPMC  READ PAGE MAP CONTROL REGISTER
          LDM    RDATA+1     CHECK BIT 8 OR 9 DEPENDING ON CPU NUMBER
          LPML   CMPA,T1
          UJN    CMPX        RETURN

 CMPA     CON    0#80,0#40   SET CPU PORT DISABLE BIT MASK
 DBC      SPACE  4,10
**        DBC - DISABLE BOUNDS CHECKING.
*
*         ENTRY  MEMORY BOUNDS ENABLED ON CERTAIN PORTS.
*
*         EXIT   MEMORY BOUNDS CHECKING DISABLED ON ALL PORTS.
*                (MBPS) = SAVED PORT SELECT VALUE.
*
*         MACROS LOCKMR, READMR, WRITMR.


 DBC      SUBR               ENTRY/EXIT
          LOCKMR SET         ACQUIRE INTERLOCK
          LDN    S0MBD       INITIALIZE REGISTER LOOP
          STD    RN
 DBC1     READMR RDATA,CMCC  READ NEXT REGISTER
          LDM    RDATA+2
          LPN    1
          SHN    5
          STM    MBPS        SAVE BIT 23
          LDM    RDATA+2
          SCN    1           CLEAR BIT 23
          STM    RDATA+2
          LDM    RDATA+3
          SHN    -3
          LMM    MBPS        ADD BITS 24 - 28 TO SAVED SELECT BITS
          STM    MBPS
          LDM    RDATA+3
          LPN    7           CLEAR BITS 24 - 28
          STM    RDATA+3
          WRITMR RDATA,CMCC  REWRITE REGISTER
          AOD    RN          ADVANCE TO NEXT REGISTER
          LMC    S0MBD+0#10
          NJP    DBC1        IF MORE BOUNDS REGISTERS TO PROCESS
          LOCKMR CLEAR       RELEASE INTERLOCK
          LJM    DBCX        RETURN
 EBC      SPACE  4,10
**        EBC - ENABLE BOUNDS CHECKING.
*
*         ENTRY  MEMORY BOUNDS DISABLED.
*                (MBPS) = SAVED PORT SELECT.
*
*         EXIT   MEMORY BOUNDS RESTORED TO PREVIOUS VALUE.
*
*         MACROS LOCKMR, READMR, WRITMR.


 EBC      SUBR               ENTRY/EXIT
          LOCKMR SET         ACQUIRE INTERLOCK
          LDN    S0MBD       INITIALIZE REGISTER LOOP
          STD    RN

*         NOTE - CODE ASSUMES THAT PORT SELECT IS IDENTICAL FOR ALL.

 EBC1     READMR RDATA,CMCC  READ NEXT REGISTER
          LDM    RDATA+2
          SCN    1
          LDM    MBPS        GET PORT ENABLE BITS
          SHN    -5
          LMM    RDATA+2     RESTORE BIT 23
          STM    RDATA+2
          LDM    RDATA+3
          LPN    7           ENSURE CLEAR
          STM    RDATA+3
          LDM    MBPS        GET ENABLE BITS
          LPN    0#1F        JUST 24 - 28
          SHN    3           POSITION
          LMM    RDATA+3     RESTORE BITS
          STM    RDATA+3
          WRITMR RDATA,CMCC
          AOD    RN          ADVANCE TO NEXT REGISTER
          LMC    S0MBD+0#10
          NJP    EBC1        IF MORE BOUNDS REGISTERS TO PROCESS
          LOCKMR CLEAR       RELEASE INTERLOCK
          LJM    EBCX        RETURN
 HTO      SPACE  4,10
**        HTO - HARDWARE TIMEOUT.
*
*         *HTO* IS CALLED EVERY 100 MSEC.
*
*         EXIT   (TFLG) = 1.


 HTO      SUBR               ENTRY/EXIT
          LDN    1           INDICATE 100 MSEC ELAPSED
          STM    TFLG
          UJN    HTOX        RETURN
 PII      SPACE  4,10
**        PII - PRESET IOU INFORMATION.
*
*         THIS IS A DUMMY ROUTINE ON S0/S0E.


 PII      SUBR               ENTRY/EXIT
          UJN    PIIX        RETURN
 SPB      SPACE  4,10
**        SPB - SET PP BOUNDS.
*
*         THIS IS A DUMMY ROUTINE ON S0/S0E.


 SPB      SUBR               ENTRY/EXIT
          UJN    SPBX        RETURN
 TIM      SPACE  4,10
**        TIM - MAINTAIN MILLISECOND TIME AND EXECUTE TIMED ROUTINES.
*
*         *TIM* USES THE CHANNEL 14 CLOCK TO ALLOW THE EXECUTION OF
*         CERTAIN ROUTINES ON A TIMED BASIS.  THE ROUTINES TO BE
*         ACTIVATED PERIODICALLY ARE IN *ACTB*.  TO ENSURE ACCURACY,
*         *TIM* SHOULD BE CALLED AT LEAST EVERY TWO MILLISECONDS.
*         FOR ACCURACY, THE 16 BIT WIDE CHANNEL 14 CLOCK IS PROCESSED IN ITS
*         ENTIRETY, RATHER THAN TRUNCATING IT TO 12 BITS FOR COMPATIBILITY.
*
*         EXIT   (TIMA) IS WITHIN ONE MILLISECOND OF CHANNEL 14 VALUE.
*
*         USES   T1, T7.
*
*         CALLS  SEE *ACTB*.
*
*         NOTE   CHANGES TO THIS ROUTINE SHOULD BE MADE IN *SCI* ALSO.


 TIM      SUBR               ENTRY/EXIT
 TIM1     IAN    14          READ MICROSECOND COUNTER
          SBML   TIMA
          PJN    TIM2        IF NO OVERFLOW
          ADC    200000
 TIM2     ADC    -1000D
          MJN    TIMX        IF LESS THAN ONE MILLISECOND ELAPSED
          LDC    1000D       ADVANCE BASE TIME BY ONE MILLISECOND
          RAML   TIMA
          AOM    TIMB        ADVANCE SCAN COUNTER
          LMN    5
          NJN    TIM1        IF SCAN PERIOD NOT UP
          STM    TIMB        RESET SCAN COUNTER
          LDC    ACTB        PRESET ACTION ENTRY
          STD    T7
          STM    TIMF
 TIM3     AOM    2,T7        ADVANCE ENTRY COUNTER
          SBM    1,T7
          MJN    TIM4        IF DELAY NOT COMPLETE
          LDN    0
          STM    2,T7        RESET COUNTER
          LDIL   T7          CALL SPECIFIED ROUTINE
          STDL   T1
          RJM    0,T1
 TIM4     LDN    3           ADVANCE TABLE INDEX
          RAM    TIMF
          STD    T7
          LMC    ACTBL
          NJN    TIM3        IF MORE ENTRIES TO CHECK
          LJM    TIM1        RETURN

 TIMF     BSS    1           FWA OF ENTRY BEING PROCESSED
*COPYC CTP$DFT_RESIDENT_II_COMMON
 COMMON   SPACE  4,10
**        COMMON DECKS.


*COPYC DSI$PACK_UNPACK_REGISTERS

          USE    OVERFLOW
          ERRNG  20000-*     RESIDENT II OVERFLOWS PP MEMORY
*COPYC CTP$DFT_PRESET_BUILD_STRUCTURE
          OVERLAY (STANDARD PRESET OVERLAY ROUTINES)
*COPYC CTP$DFT_PRESET_STANDARD_OVL
 SSO      SPACE  4,10
**        SSO - PRESET  SPECIAL OVERLAY FOR IOU BIT 57 ERROR.
*         NON OPERATIONAL HERE.


 SSO      SUBR
          UJN    SSOX        RETURN

 GMI      SPACE  4,10
**        GMI - GET MEMORY INSTALLED.
*
*         EXIT   (NBRDS) = NUMBER OF BOARDS PRESENT.
*
*         USES   T0, T1.


 GMI      SUBR               ENTRY/EXIT
          READMR RDATA,I0CC,OIMR  CHECK BOARD CONFIGURATION IN IOU *OI*
          LDML   RDATA+2     CHECK *OI* BIT 16
          STDL   T0
          SHN    -7
          STD    T1
          LDDL   T0          CHECK *OI* BIT 17
          SHN    -6
          LPN    1
          RAD    T1
          LDDL   T0          CHECK *OI* BIT 18
          SHN    -5
          LPN    1
          RAD    T1
          LDDL   T0          CHECK *OI* BIT 19
          SHN    -4
          LPN    1
          ADD    T1
          STM    NBRDS       STORE RESULT

*         NEXT FIND OUT IF MEMORY HAS BEEN DEGRADED. IF IT HAS WHICH
*         SET OF BANKS HAS BEEN DEGRADED. POSSIBILITIES ARE (0,1) (2,3).
*         THE HARDWARE ASSUMES DEGRADED BANKS AS (0,1).

          READMR RDATA,CMCC,ECMR  MEMORY *DEC* REGISTER
          LDM    RDATA
          LPN    6           GET JUST RECONFIGURATION BITS 5-6
          ZJP    GMIX        IF NO RECONFIGURATION
          STD    T1          SAVE RECONFIGURATION BITS
          LDN    2
          STM    NBNK        NUMBER OF BANKS TO SEARCH GOES TO 2 IF RECONFIG
          LDD    T1
          LPN    2
          NJP    GMIX        IF LOWER TWO BANKS
          LDN    2
          STM    SBNK        IF USE UPPER TWO BANKS
          STM    DEGR        SET UP OFFSET W/MEMORY DEGRADED (BANKS 2,3 ARE 0,1)
          LDN    4
          STM    NBNK        FOR UPPER TWO BANKS (2,3)
          LJM    GMIX        RETURN
*COPY CTP$DFT_RETURN_ERROR_CODE
 SMV      SPACE  4,10
**        SMV - SET UP MODEL DEPENDENT VALUES.
*
*         *SMV* WILL SET UP REGISTER LIST ADDRESSES ON A MODEL DEPENDENT BASIS, AND
*         AND WILL INITIALIZE ALL MODEL DEPENDENT GLOBAL DATA.
*
*         EXIT   (CLST2) = 1 IF BOTH CLUSTERS 0 AND 2 PRESENT.
*                (PMEI) = PAGE MAP ELEMENT INDEX.
*                (S0FLG) = 1.
*                (S0EFLG) = 1 IF MAINFRAME IS S0E (MODEL 54/55).
*                (S0PMC) = PAGE MAP CONNECT CODE.
*                PROCESSOR REGISTER NUMBERS INITIALIZED.
*                REGISTER LISTS SET UP.
*                *2AP* VALUES INITIALIZED.


 SMV      SUBR               ENTRY/EXIT

*         SET UP IOU REGISTER LISTS.

          READMR RDATA,I0CC,OIMR  READ OPTIONS INSTALLED
          LDM    RDATA       CHECK *OI* BIT 1 FOR CLUSTER 2 PRESENT
          LPC    0#40
          NJN    SMV1        IF CLUSTERS 0 AND 2 ARE PRESENT
          LDC    RLUIE0      UNCORRECTED REGISTER LIST FOR CLUSTER 0
          STM    IO0U
          LDC    RLCIE0      CORRECTED REGISTER LIST FOR CLUSTER 0
          STM    IO0C
          UJN    SMV2        SET UP MEMORY LISTS

 SMV1     LDC    RLUIE2      UNCORRECTED REGISTER LIST FOR CLUSTERS 0/2
          STM    IO0U
          LDC    RLCIE2      CORRECTED REGISTER LIST FOR CLUSTERS 0/2
          STM    IO0C
          LDN    1           SET FLAG FOR TWO CLUSTERS
          STM    CLST2

*         SET UP MEMORY REGISTER LISTS.

 SMV2     LDC    RLUME       SET UNCORRECTED MEMORY ERROR LIST
          STM    ME0U
          LDC    RLCME       SET CORRECTED MEMORY ERROR LIST
          STM    ME0C
          LDN    1           SET S0/S0E FLAG TRUE
          STM    S0FLG
          RJM    GMI         DETERMINE MEMORY BOARD CONFIGURATION

*         SET UP PAGE MAP INFORMATION.

          LDN    PMID        READ PAGE MAP MRT
          RJM    FHE
          MJP    SMV5        IF NOT FOUND
          STM    PMEI        SAVE PAGE MAP ELEMENT INDEX
          LDM    HBUF+HDRPC  GET PAGE MAP CONNECT CODE
          STM    S0PMC

*         DETERMINE PROCESSOR TYPE (S0 OR S0E).

          AOM    S0FLG       SET S0/S0E FLAG
          LDN    0           SET PORT OFFSET
          STD    PO
          LDM    CPU0M       CHECK CPU MODEL
          LPN    0#F
          STD    T1
          LDM    SMVA,T1     GET S0/S0E FLAG
          NJN    SMV2.5      IF CPU MODEL DEFINED
          SETDAN (EPUN,DAMD)
          LDC    DAMD+TDFT   608 - INCOMPATABLE HARDWARE MODEL
          CALL   ERRH

 SMV2.5   SBN    1
          NJN    SMV3        IF S0E

*         SET UP S0 PROCESSOR REGISTER LISTS.

          LDC    RLUPE       SET UNCORRECTED PROCESSOR ERROR LIST
          STM    CP0U
          STM    CP1U
          LDC    RLCPE       SET CORRECTED PROCESSOR ERROR LIST
          STM    CP0C
          STM    CP1C
          UJN    SMV4        CONTINUE

*         SET UP S0E PROCESSOR REGISTER LISTS.

 SMV3     LDC    /S0E/RLUPE  SET S0E UNCORRECTED PROCESSOR ERROR LIST
          STM    CP0U
          STM    CP1U
          LDC    /S0E/RLCPE  SET S0E CORRECTED PROCESSOR ERROR LIST
          STM    CP0C
          STM    CP1C
          AOM    S0EFLG      SET S0E FLAG
 SMV4     LJM    SMVX        RETURN

*         PROCESS DESCRIPTOR NOT FOUND IN MRT.

 SMV5     SETDAN (EPUN,DAME)
          LDC    DAME+TDFT   613 - DFT NO DESC IN MRT
          STML   RTP1
          CALL   ERRH

 SMVA     CON    1           CPU MODEL 50 IS AN S0
          CON    1           CPU MODEL 51 IS AN S0
          CON    1           CPU MODEL 52 IS AN S0
          CON    1           CPU MODEL 53 IS AN S0
          CON    2           CPU MODEL 54 IS AN S0E
          CON    2           CPU MODEL 55 IS AN S0E
          CON    0           CPU MODEL 56 IS RESERVED
          CON    0           CPU MODEL 57 IS RESERVED
          CON    0           CPU MODEL 58 IS RESERVED
          CON    0           CPU MODEL 59 IS RESERVED
          CON    0           CPU MODEL 5A IS RESERVED
          CON    1           CPU MODEL 5B IS AN S0
          CON    2           CPU MODEL 5C IS AN S0E
          CON    1           CPU MODEL 5D IS AN S0
          CON    1           CPU MODEL 5E IS AN S0
          CON    2           CPU MODEL 5F IS AN S0E

*COPYC CTP$DFT_PRESET_PACKETS
*COPY     CTP$DFT_NO_CLEAR_PACKETS
          OVERLAY  (MAIN NON-RESIDENT ROUTINES)
 NONRES   SPACE  4,10
**        START OF THE MAIN NON RESIDENT ROUTINES OVERLAY.
*
*         ON S0/S0E, THIS OVERLAY DEFINES ROUTINES FOR PACKETS, NON I4,
*         HALT ON ERROR PROCESSING, EICB TIME UPDATE, AND PACKET COMMUNICATION.
*COPYC CTP$DFT_MAIN_NON_RES_RTNS
*COPYC CTP$DFT_MAIN_NON_RES_NON_I4
*COPYC CTP$DFT_MAIN_NON_RES_EICB_TIME
*COPYC CTP$DFT_CHECK_PACKET_STATUS
*COPY CTP$DFT_CHECK_PKT_ERROR_STATUS
*COPY CTP$DFT_CHECK_PKTS_FOR_S0
*COPY CTP$DFT_LOG_PACKET_TIMEOUT
*COPYC CTP$DFT_PP_REQUESTS_RELOCATION
 BCA      SPACE  4,10
**        BCA - HANDLE BLOCKED CM ACCESS.
*         THIS IS VALID ON A MODEL 44, 43 IOU ONLY. (STUB HERE)
          QUAL   HB57


 BCA      SUBR
          UJN    BCAX        RETURN
          QUAL   *
 RSP      SPACE  4,10
**        RSP - RESTART SCI PP.
*
          ROUTINE RSP
          RJM    LRP
          CRDL   W0          GET PARAMETERS
          LDDL   W2          GET PP NUMBER
          SHN    -10
          STD    W0          SET UP FOR *RJM* TO *RSC*
          RJM    RSC         RELOCATE SCI TO SAME PP
          LJM    RSPX        RETURN

*COPY CTP$DFT_PREPARE_FOR_CIP_CALL
*COPY CTP$DFT_RETURN_ERROR_CODE
*COPYC CTP$DFT_CPU_HANDSHAKER

 HOE      SPACE  4,10
**        HOE - HALT ON ERROR.
*
*         EXIT   HALT-ON-ERROR SET IN PROCESSOR *DEC* REGISTER.
*
*         CALLS  SHE.
*
*         MACROS LOCKMR.


          ROUTINE  HOE

          LOCKMR SET         ACQUIRE INTERLOCK
          LDN    PROCID      READ MRT ENTRY FOR CPU-0
          RJM    SHE         SET HALT-ON-ERROR
          LDC    PROCID1     READ MRT ENTRY FOR CPU-1
          RJM    SHE         SET HALT-ON-ERROR
          LOCKMR CLEAR       RELEASE INTERLOCK
          LJM    HOEX        RETURN
 SHE      SPACE  4,10
**        SHE - SET HALT-ON-ERROR.
*
*         ENTRY  (A) = HARDWARE ELEMENT TO PROCESS.
*
*         EXIT   HALT-ON-ERROR SET IN CPU *DEC* REGISTER.
*
*         CALLS  FHE.
*
*         MACROS READMR, WRITMR.


 SHE      SUBR               ENTRY/EXIT
          RJM    FHE         READ MRT ENTRY
          MJN    SHEX        IF ELEMENT NOT FOUND
          LDM    HBUF+CPRSTAT+PSCPOFF  CHECK CPU STATUS
          LPN    1
          NJN    SHEX        IF CPU DOWN
          LDM    S0EFLG      CHECK MAINFRAME TYPE
          NJN    SHE1        IF S0E

*         SET HALT-ON-ERROR FOR S0 CPU.

          READMR RDATA,HBUF+CPRPC,S0PCSD  READ CPU *DEC* REGISTER
          LDM    RDATA+4
          SCN    0#20
          LMN    0#20
          STM    RDATA+4
          UJN    SHE2        CONTINUE

*         SET HALT-ON-ERROR FOR S0E CPU.

 SHE1     READMR RDATA,HBUF+CPRPC,SEPCSC  READ CONTROL STORE CONTROL REGISTER
          LDM    RDATA+1
          SCN    0#20
          LMN    0#20
          STM    RDATA+1

*         COMMON EXIT.

 SHE2     WRITMR RDATA,HBUF+CPRPC REWRITE *DEC* REGISTER
          LJM    SHEX        RETURN


 RED      SPACE  4,10
**        RED - READ 960 POWER MONITOR.
*
*         ON ANY MACHINE OTHER THAN THE 960 THIS ROUTINE IS
*         NON FUNCTIONAL.


          ROUTINE RED
          LJM    REDX

          OVERFLOW  10000    CHECK FOR OVERFLOW
          OVERLAY  (DO DFT ACTIONS)
*COPYC CTP$DFT_ACTION_LIST
*COPYC CTP$DFT_ACTION_LIST_OVERFLOW

 S1PG     BSS    0           START 170 PROCESSOR
          TASK   (RRE)       RETURN REQUEST ERROR - NOT USED ON S0/S0E

 H1PG     BSS    0           HALT 170 PROCESSOR
          TASK   (RRE)       RETURN REQUEST ERROR - NOT USED ON S0/S0E

 HVPG     BSS    0           TERMINATE ALL VIRTUAL PROCESSORS
          TASK   (PCP)

 DCEMP    BSS    0           CLEAR PAGE MAP AND PROCESSOR ERRORS
          TASK   (CPE,CLE,SPR)

 IAPP     BSS    0           IDLE ALL PP-S IN IOU-1
          TASK   (RRE)       RETURN REQUEST ERROR - NOT USED ON S0/S0E

 DDCE     BSS    0           CLEAR ERROR ON S0/S0E
          TASK   (CLE,SPR)   CLEAR ERROR AND START CPU
          QUAL   *
*COPYC CTP$DFT_RETURN_TASK_ERROR
          QUAL   ABC
*COPY CTP$DFT_RETURN_ERROR_CODE
          QUAL   *

          QUAL   *

          OVERFLOW  10000    CHECK FOR OVERFLOW
          OVERLAY (SAVE PP REGISTERS IN CENTRAL MEMORY)
*COPYC CTP$DFT_SAVE_PP_REGISTERS
*COPY  CTP$DFT_930_DUMP_PP_REGS
          OVERFLOW 10000     CHECK FOR OVERFLOW
          OVERLAY  (DFT ERROR CONTROL OVERLAY)
*COPYC CTP$DFT_ERROR_CONTROL

          OVERFLOW  10000    CHECK FOR OVERFLOW
          OVERLAY  (LOG TOP OF HOUR COUNTERS)
*COPYC CTP$DFT_LOG_COUNTERS
 RMC      SPACE  4,10
**        RMC - RESET MODEL DEPENDENT COUNTERS.
*
*         THIS IS A DUMMY ROUTINE ON S0/S0E.


          ROUTINE RMC        ENTRY/EXIT
          LJM    RMCX        RETURN

 RMCF     CON    0
*COPY     CTP$DFT_NO_RESET_PIT
*COPY     CTP$DFT_NO_TEST_DLD_PATH

          OVERFLOW  10000    OVERFLOW
          OVERLAY  (ENVIRONMENT/SHORT WARNING PROCESSORS)
*COPYC CTP$DFT_ENVIRONMENT_RTNS
*COPY  CTP$DFT_FIND_WARNING_IN_NRSB
 CCA      SPACE  4,10
**        CCA - CHECK IF CONSOLE IS ALIVE.
*
*         EXIT   A = 0, IF CONSOLE HAS NO POWER.
*                A > 0, IF CONSOLE HAS POWER.
*
*         USES   SCF.


 CCA      SUBR               ENTRY/EXIT
          LDN    MX          MUX CHANNEL
          RJM    SCF         SET CHANNEL FLAG
          DCN    MX+40       DEACTIVATE TPM CHANNEL
          LDN    MXSS        MUX STATUS
          FAN    MX
          LCN    0
 CCA3     SBN    1
          ZJN    CCA4        IF TIMED OUT, REPORT CONSOLE NOT ALIVE
          AJM    CCA3,MX     IF FUNCTION NOT ACCEPTED YET
          ACN    MX          GET TPM STATUS
          IAN    MX
          LPN    6           EXTRACT DATA SET READY, CARRIER ON
 CCA4     DCN    MX+40
          CCF    *,MX        RELEASE CHANNEL INTERLOCK
          LJM    CCAX        RETURN
          QUAL   *

          OVERFLOW  10000    CHECK FOR OVERFLOW
          OVERLAY  (ANALYZE PROCESSOR ERROR)
 APE      SPACE  4,10
**        APE - ANALYZE PROCESSOR ERROR.
*
*         ENTRY  SUMMARY STATUS INDICATES PROCESSOR ERROR.
*                (EC) = CONNECT CODE FOR AFFECTED PROCESSOR.
*                (ET) = *PROCID*.
*                (CPUO) = CPU ORDINAL FOR AFFECTED PROCESSOR.
*                (SUMS) = SUMMARY STATUS.
*
*         EXIT   TO *CCE* IF CORRECTED ERROR.
*                TO *DCE* IF CPU DEAD.
*                TO *PCE* IF DUE ERROR.
*                TO *RFI* TO RETRY FAILING INSTRUCTION.
*                TO *SPR* TO RESTART PROCESSOR.
*                TO *SWP* IF SHORT WARNING INDICATED.
*                TO *UCE* IF UNCORRECTED ERROR.
*
*         CALLS  CLR, CMH, HPR, PCS, REL, *CFF*, *SWP*.
*
*         MACROS READMR.


          ROUTINE  APE

          LDN    0           SET NO ERROR FLAG FALSE
          STM    NERR
          STM    RETRYC      SET RETRY COUNTER = 0 AND *DUETRAP* = FALSE
          STM    DUETRAP

*         SET CPU RETRY LIMIT.
*
*         NOTE - THIS CODE LOGICALLY BELONGS IN *PRS*.  IT IS LOCATED
*         HERE SINCE THE RETRY LIMIT MUST BE CHANGED DURING TESTING,
*         WHICH WOULD REQUIRE REDEADSTARTING IF IT WERE SAVED IN *PRS*.

          LDM    S0EFLG      CHECK MAINFRAME TYPE
          NJN    APE1        IF S0E

*         SET S0 RETRY LIMIT.

          READMR RDATA,CP0CC,S0PPRC  READ PFS/RETRY CONTROL REGISTER
          LDM    RDATA+1     EXTRACT RETRY LIMIT FROM BITS 10-13
          UJN    APE2        CONTINUE

*         SET S0E RETRY LIMIT.

 APE1     READMR RDATA,CP0CC,SEPRPR  READ REGISTER FILE PFS AND RETRY REGISTER
          LDM    RDATA+3     EXTRACT RETRY LIMIT FROM BITS 26-29

*         RESUME COMMON PROCESSING.

 APE2     SHN    -2
          LPN    17
          ADN    1           SAVE LIMIT + 1
          STM    RETRYL

*         IT IS NECESSARY TO SAVE THE PRE-HALT SUMMARY STATUS BECAUSE
*         HALTING THE PROCESSOR WILL SET THIS BIT.  ROUTINE *RMR* USES
*         THE *OLSS* VALUE WHEN BUILDING THE SCRATCH MRB.

          LDM    SUMS        SAVE PRE-HALT SUMMARY STATUS FOR *RMR*
          STM    OLSS
          SHN    21-SSSW     CHECK FOR SHORT WARNING
          PJN    APE3        IF NO SHORT WARNING
          CALL   SWP         CALL SHORT WARNING PROCESSOR
          LJM    APEX        RETURN

*         REENTER HERE AFTER CPU IS RESTARTED.

 APE3     LDM    CPUO        SAVE HALTED CPU ORDINAL
          STM    CPUH
          RJM    HPR         HALT PROCESSOR
          LDN    1
          RJM    SCS         SAVE AFTER HALT CSA AND SS REGISTERS FOR SUPPORTIVE STATUS
          RJM    PCS         PACK CONTROL STORE ADDRESSES
          RJM    REL         READ UNCORRECTED AND FIRST/CORRECTED ERROR LOGS
          CALL   CFF         CHECK IF FREEZE ON ERROR WANTED
          LDN    BC          CLEAR SCRATCH BUFFER CONTROL WORD
          RJM    CLR

*         CHECK FOR FATAL ERROR - BITS 46/47 OF REGISTER 0#881 NONZERO.

          LDML   PUEL+1*4+2  CHECK UNCORRECTED ERROR LOG
          LPN    3
          NJP    PCE         IF FATAL CPU ERROR

*         CHECK FOR *DUE* ERRORS.

          LDM    SUMS        CHECK FOR *DUE*
          SHN    21-SSUE
          PJP    APE6        IF *DUE* NOT SET
          LDML   CSA0        CHECK CONTROL STORE ADDRESS
          LMC    0#100
          ZJP    APE5        IF RETRYABLE ERROR (CONTROL STORE ADDRESS = 100)
          LMN    0#105&0#100
          ZJP    APE5        IF RETRYABLE ERROR (CONTROL STORE ADDRESS = 105)
          RJM    CMH         CHECK MICROHALT (CONTROL STORE ADDRESSES 141 - 158)
          NJN    APE4        IF NOT MICROHALT

*         SET UP SCRATCH BUFFER CONTROL WORD.
*
*         DFT ANALYSIS - ANALYSIS = CPU DEAD - MICROCODE HALT.
*         DFT ANALYSIS - DFT ACTION = DISABLE CPU.
*         DFT ANALYSIS - ERROR PRIORITY = UNCORRECTED ERROR.
*         DFT ANALYSIS - FLAGS = LOG (CONSOLE), LOG (OS).

          SETDAC (DDDC)
          SETDAN (EPUN,DADMH)
          SETFLG (BC.CL,BC.FL)
          LJM    DCE         PROCESS DEAD CPU

 APE4     LDM    DUETRAP     CHECK *DUETRAP*
          ZJP    PCE         IF DUETRAP NOT SET, PROCESS FATAL CPU ERROR
          LJM    UCE         PROCESS UNCORRECTED CPU ERROR

*         SET UP TO RETRY INSTRUCTION.

 APE5     LDN    1           SET DUETRAP AND RETRY
          STM    DUETRAP
          LJM    SPR         START PROCESSOR

*         CHECK FOR CORRECTED ERROR.

 APE6     LDML   CSA0        CHECK CONTROL STORE ADDRESS
          LMC    0#105
          ZJP    RFI         IF MICROCODE READY FOR RETRY
          RJM    CMH         CHECK MICROHALT (CONTROL STORE ADDRESSES 141 - 158)
          NJP    APE8        IF NOT MICROHALT
          LDML   CSA2        CHECK FOR MCR/UCR HALT
          LMC    0#151
          ZJN    APE7        IF CLASS II HALT

*         SET UP SCRATCH BUFFER CONTROL WORD.
*
*         DFT ANALYSIS - ANALYSIS = CPU DEAD - UNEXPECTED MICROHALT ADDRESS.
*         DFT ANALYSIS - DFT ACTION = DISABLE CPU.
*         DFT ANALYSIS - ERROR PRIORITY = UNCORRECTED ERROR.
*         DFT ANALYSIS - FLAGS = LOG (CONSOLE), LOG (OS).

          SETDAC (DDDC)
          SETDAN (EPUN,DADUA)
          SETFLG (BC.CL,BC.FL)
          LJM    DCE         PROCESS DEAD CPU

*         SET UP SCRATCH BUFFER CONTROL WORD.
*
*         DFT ANALYSIS - ANALYSIS = CLASS II HALT.
*         DFT ANALYSIS - DFT ACTION = DISABLE CPU.
*         DFT ANALYSIS - ERROR PRIORITY = UNCORRECTED ERROR.
*         DFT ANALYSIS - FLAGS = LOG (CONSOLE), LOG (OS).

 APE7     SETDAC (DDDC)
          SETDAN (EPUN,DASWH)
          SETFLG (BC.CL,BC.FL)
          LJM    DCE         PROCESS DEAD CPU

 APE8     LDM    SUMS        CHECK FOR CORRECTED ERROR
          SHN    21-SSCE
          MJP    CCE         PROCESS CORRECTED CPU ERROR

*         SET UP SCRATCH BUFFER CONTROL WORD.
*
*         DFT ANALYSIS - ANALYSIS = CPU DEAD - NO ERROR DETECTED.
*         DFT ANALYSIS - DFT ACTION = DISABLE CPU.
*         DFT ANALYSIS - ERROR PRIORITY = UNCORRECTED ERROR.
*         DFT ANALYSIS - FLAGS = LOG (CONSOLE), LOG (OS).

          SETDAC (DDDC)
          SETDAN (EPUN,DADNE)
          SETFLG (BC.CL,BC.FL)
          LJM    DCE         PROCESS DEAD CPU
 CCE      SPACE  4,10
**        CCE - PROCESS CORRECTED CPU ERROR.
*
*         DFT ANALYSIS - ANALYSIS = CORRECTED PROCESSOR ERROR.
*         DFT ANALYSIS - DFT ACTION = CLEAR ERROR.
*         DFT ANALYSIS - ERROR PRIORITY = CORRECTED ERROR.
*         DFT ANALYSIS - FLAGS = LOG (OS).


 CCE      BSS    0           ENTRY
          LDM    PFCL+1*4+1  CHECK BIT 23 OF REGISTER #891
          LPC    0#100
          ZJN    CCE1        IF NO PAGE MAP ERROR RESPONSE
          LDN    SSMR        CHECK FOR PAGE MAP ERROR IN MEMORY SUMMARY STATUS
          STD    RN
          LDM    CMCC        READ MEMORY SUMMARY STATUS
          RJM    RMR
          SHN    21-SSPM
          MJP    CME         IF CORRECTED PAGE MAP ERROR
          LDM    HBUF+CPRPC  RESTORE PROCESSOR CONNECT CODE
          STD    EC
 CCE1     SETDAC (DDCE)
          SETDAN (EPCO,DACPE)
          SETFLG (BC.FL)
          RJM    SCL         SET CORRECTED LIST TO BE LOGGED
          LJM    UML         UPDATE MRB AND LOG ERROR
 CME      SPACE  4,10
**        CME - PROCESS CORRECTED PAGE MAP ERROR.
*
*         DFT ANALYSIS - ANALYSIS = CORRECTED PAGE MAP ERROR.
*         DFT ANALYSIS - DFT ACTION = CLEAR ERRORS IN PAGE MAP AND CPU.
*         DFT ANALYSIS - ERROR PRIORITY = CORRECTED ERROR.
*         DFT ANALYSIS - FLAGS = LOG (OS).


 CME      BSS    0           ENTRY
          RJM    SML         SET PAGE MAP REGISTER LIST
          SETDAC (DCEMP)
          SETDAN (EPCO,DACPM)
          SETFLG (BC.FL)
          CALL   RMR         READ MAINTENANCE REGISTERS
          LJM    UML1        UPDATE MRB AND LOG ERROR
 DCE      SPACE  4,10
**        DCE - PROCESS DEAD CPU ERROR.
*
*         CALLS  SUL.


 DCE      BSS    0           ENTRY
          RJM    SUL         SET UNCORRECTED LIST TO BE LOGGED
          LJM    UML         UPDATE MRB AND LOG ERROR
 PCE      SPACE  4,10
**        PCE - PROCESS CPU ERROR.
*
*         DFT ANALYSIS - ANALYSIS = UNCORRECTED PROCESSOR ERROR.
*         DFT ANALYSIS - DFT ACTION = CLEAR ERRORS.
*         DFT ANALYSIS - ERROR PRIORITY = UNCORRECTED ERROR.
*         DFT ANALYSIS - FLAGS = LOG (CONSOLE), LOG (OS).


 PCE      BSS    0           ENTRY
          SETDAC (DDCE)
          SETDAN (EPUN,DAUPE)
          SETFLG (BC.CL,BC.FL)
          RJM    CCU         CHECK FOR CONTROL STORE UNCORRECTED ERROR
 PCE0     NJP    RCM         IF CONTROL STORE RELOAD NECESSARY

*         READ AND SAVE EXCHANGE PACKAGE ADDRESS, SINCE IT WILL NOT BE
*         POSSIBLE TO READ *JPS*/*MPS* AFTER THE HALF-EXCHANGE OUT.

 PCE0.1   LDC    0#1A4       RESTART CPU TO ALLOW *MPS* AND *JPS* ACCESS
          RJM    SMC         START MICROCODE
          LDM    SUMS        DETERMINE MODE OF CPU
          LPN    0#20
          NJN    PCE1        IF MONITOR MODE
          READMR RDATA,,S0PJPS  READ ADDRESS OF JOB MODE EXCHANGE PACKAGE
          UJN    PCE2        CONTINUE

 PCE1     READMR RDATA,,S0PMPS  READ ADDRESS OF MTR MODE EXCHANGE PACKAGE
 PCE2     RJM    PAC         PACK (RDATA - RDATA+7) INTO (MRVAL)
          CALL   HEO         HALF-EXCHANGE OUT
          LDML   MRVAL       VALIDATE EXCHANGE PACKAGE ADDRESS
          LMC    0#FFFF
          ZJP    PCE4        IF EXCHANGE PACKAGE ADDRESS NOT AVAILABLE
          READMR RDATA,,S0PCSA  REREAD CONTROL STORE ADDRESSES
          LDM    RDATA+6     PACK *S2* ADDRESS
          SHN    10
          ADM    RDATA+7
          LMC    0#142
          NJP    PCE4        IF HALF-EXCHANGE OUT FAILED

*         CHECK *PND* FLAG IN EXCHANGE PACKAGE IN CM, AND IF SET,
*         CLEAR *DUE* IN *MCR* OF EXCHANGE PACKAGE IN CM.

          CALL   SRA         CONVERT (MRVAL) TO R-POINTER IN (W4 - W6)
          LRD    W4
          LDDL   W6          READ WORD 2 OF EXCHANGE PACKAGE IN CM
          ADC    RR+2
          CRDL   CM
          LDDL   CM          CHECK FOR PROCESS NOT DAMAGED STATUS
          LPC    0#1000
          ZJP    PCE4        IF *PND* NOT SET
          LDDL   W6          READ *MCR* WORD OF EXCHANGE PACKAGE
          ADC    RR+6
          CRDL   CM
          LDDL   CM+3        CLEAR *DUE* BIT
          LPC    0#7FFF
          STDL   CM+3
          LDDL   W6          REWRITE *MCR* WORD OF EXCHANGE PACKAGE IN CM
          ADC    RR+6
          CWDL   CM
          LDM    SUMS        CHECK MODE OF CPU
          LPN    0#20
          ZJN    PCE2.1      IF NOT MONITOR MODE
          LDN    0
          UJN    PCE3        CONTINUE

 PCE2.1   LDN    0#1A3-0#1A2
 PCE3     ADC    0#1A2
          RJM    SMC         START MICROCODE
          RJM    SCL         SET CORRECTED REGISTER LIST
          LJM    UML         UPDATE MRB AND LOG ERROR

 PCE4     LDM    SUMS        CHECK FOR MONITOR MODE
          LPN    0#20
          ZJP    PCE3        IF NOT MONITOR MODE

*         SET UP SCRATCH BUFFER CONTROL WORD.
*
*         DFT ANALYSIS - ANALYSIS = CPU DEAD - MONITOR MODE DUE.
*         DFT ANALYSIS - DFT ACTION = DISABLE CPU.
*         DFT ANALYSIS - ERROR PRIORITY = UNCORRECTED ERROR.
*         DFT ANALYSIS - FLAGS = LOG (CONSOLE), LOG (OS).

          SETDAC (DDDC)
          SETDAN (EPUN,DADMD)
          SETFLG (BC.CL,BC.FL)
          LJM    DCE         PROCESS DEAD CPU
 RCM      SPACE  4,10
**        RCM - RELOAD CONTROL STORE.
*
*         NOTE   THIS REQUIRES *2AP* SUPPORT WHICH IS NOT AVAILABLE TODAY.
*                THEREFORE, IT RETURNS A RELOAD FAILED CONDITION AT THIS TIME.
*                WHEN RELOADS ARE DONE, A NORMAL EXIT IS TO PCE0.1.

 RCM      BSS    0           ENTRY

*         SET UP SCRATCH BUFFER CONTROL WORD.
*
*         DFT ANALYSIS - ANALYSIS = CPU DEAD - CONTROL STORE RELOAD FAILED.
*         DFT ANALYSIS - DFT ACTION = DISABLE CPU.
*         DFT ANALYSIS - ERROR PRIORITY = UNCORRECTED ERROR.
*         DFT ANALYSIS - FLAGS = LOG (CONSOLE), LOG (OS).

          SETDAC (DDDC)
          SETDAN (EPUN,DADRF)
          SETFLG (BC.CL,BC.FL)
          LJM    DCE         PROCESS DEAD CPU
 RFI      SPACE  4,10
**        RFI - RETRY FAILING INSTRUCTION.


 RFI      BSS    0           ENTRY
          AOM    RETRYC      INCREMENT RETRY COUNTER
          LMM    RETRYL
          NJN    SPR         IF RETRIES NOT EXHAUSTED
          STM    RETRYC

*         SET UP SCRATCH BUFFER CONTROL WORD.
*
*         DFT ANALYSIS - ANALYSIS = CPU DEAD - RETRIES EXHAUSTED.
*         DFT ANALYSIS - DFT ACTION = DISABLE CPU.
*         DFT ANALYSIS - ERROR PRIORITY = UNCORRECTED ERROR.
*         DFT ANALYSIS - FLAGS = LOG (CONSOLE), LOG (OS).

          SETDAC (DDDC)
          SETDAN (EPUN,DADRX)
          SETFLG (BC.CL,BC.FL)
          LJM    DCE         PROCESS DEAD CPU
 SPR      SPACE  4,10
**        SPR - START PROCESSOR.
*
*         MACROS FUNCMR.


 SPR      BSS    0           ENTRY
          FUNCMR ,MRSP       START PROCESSOR
          LJM    APE3        HALT PROCESSOR AND RECHECK
 UCE      SPACE  4,10
**        UCE - PROCESS UNCORRECTED CPU ERROR.
*
*         DFT ANALYSIS - ANALYSIS = UNCORRECTED PROCESSOR ERROR.
*         DFT ANALYSIS - DFT ACTION = CLEAR ERROR.
*         DFT ANALYSIS - ERROR PRIORITY = UNCORRECTED ERROR.
*         DFT ANALYSIS - FLAGS = LOG (CONSOLE), LOG (OS), VALID 180.
*         DFT ANALYSIS - OS ACTION = UNCORRECTED PROCESSOR ERROR.
*                                  = NO OS ACTION (VERSION 4).


 UCE      BSS    0           ENTRY
          LDM    PFCL+1*4+1  CHECK BIT 23 OF REGISTER #891
          LPC    0#100
          ZJN    UCE1        IF NO PAGE MAP ERROR RESPONSE
          LDN    SSMR        CHECK FOR PAGE MAP ERROR IN MEMORY SUMMARY STATUS
          STD    RN
          LDM    CMCC        READ MEMORY SUMMARY STATUS
          RJM    RMR
          SHN    21-SSPM
          MJP    UME         IF UNCORRECTED PAGE MAP ERROR
          LDM    HBUF+CPRPC  RESTORE PROCESSOR CONNECT CODE
          STD    EC
 UCE1     SETDAC (DDCE)
          SETDAN (EPUN,DAUPE)
          SETFLG (BC.CL,BC.FL,BC.FV8)
          SETOSA OSUPE,OSNA
          RJM    CCU         CHECK FOR CONTROL STORE UNCORRECTED ERROR
          NJP    PCE0        IF CONTROL STORE RELOAD NECESSARY
          RJM    SUL         SET UNCORRECTED LIST TO BE LOGGED
          LJM    UML         UPDATE MRB AND LOG ERROR
 UME      SPACE  4,10
**        UME - PROCESS UNCORRECTED PAGE MAP ERROR.
*
*         DFT ANALYSIS - ANALYSIS = UNCORRECTED PAGE MAP ERROR.
*         DFT ANALYSIS - DFT ACTION = CLEAR ERRORS IN PAGE MAP AND CPU.
*         DFT ANALYSIS - ERROR PRIORITY = UNCORRECTED ERROR.
*         DFT ANALYSIS - FLAGS = LOG (CONSOLE), LOG (OS).


 UME      BSS    0           ENTRY
          RJM    SML         SET PAGE MAP REGISTER LIST
          SETDAC (DCEMP)
          SETDAN (EPUN,DAUPM)
          SETFLG (BC.CL,BC.FL)
          CALL   RMR         READ MAINTENANCE REGISTERS
          UJN    UML1        UPDATE MRB AND LOG ERROR
 UML      SPACE  4,10
**        UML - UPDATE MRB WITH ORIGINAL ERROR LOG REGISTERS AND LOG ERROR.
*
*         ENTRY  (PUEL - PUEL+7) = ORIGINAL *S0PUEL* REGISTER CONTENTS.
*                (PFCL - PFCL+7) = ORIGINAL *S0PFCL* REGISTER CONTENTS.
*                REGISTER LIST(S) SET UP.
*
*         EXIT   SCRATCH MRB UPDATED WITH ORIGINAL REGISTER CONTENTS.
*                *LOG* CALLED.
*
*         CALLS  CID, FMB, SSE, *LOG*, *RMR*.


 UML      BSS    0           ENTRY
          CALL   RMR         READ MAINTENANCE REGISTERS TO SCRATCH MRB
          LDM    CPUO        GET CPU ORDINAL
          RJM    SSE         SET PROCESSOR ID
          LDC    S0PUEL      UPDATE UNCORRECTED ERROR LOG IN SCRATCH MRB
          RJM    FMB
          CWML   PUEL,ON
          LDC    S0PFCL      UPDATE FIRST/CORRECTED ERROR LOG IN SCRATCH MRB
          RJM    FMB
          CWML   PFCL,ON

*         PAGE MAP PROCESSING ENTERS HERE TO UPDATE ONLY 0#881/0#891.

 UML1     LDC    S0PUEL+1    UPDATE UNCORRECTED ERROR LOG IN SCRATCH MRB
          RJM    FMB
          CWML   PUEL+4,ON
          LDC    S0PFCL+1    UPDATE FIRST/CORRECTED ERROR LOG IN SCRATCH MRB
          RJM    FMB
          CWML   PFCL+4,ON
          RJM    CID         CHECK IF CPU DEGRADABLE
          CALL   LOG         LOG ERROR
          LJM    APEX        RETURN
 CCU      SPACE  4,10
**        CCU - CHECK FOR CONTROL STORE UNCORRECTED ERROR.
*
*         EXIT   (A) = 0 IF NO CONTROL STORE SECDED ERROR INDICATED.
*
*         MACROS READMR.


 CCU      SUBR               ENTRY/EXIT
          LDM    S0EFLG      CHECK MAINFRAME TYPE
          NJN    CCU1        IF S0E

*         PROCESS S0 CPU.

          READMR RDATA,,S0PCSS  CHECK CONTROL STORE SECDED ERRORS
          LDM    RDATA+2
          SHN    10
          ADM    RDATA+3
          LPC    0#5858      EXTRACT BITS 17, 19, 20, 25, 27, 28
          UJN    CCUX        RETURN

*         PROCESS S0E CPU.

 CCU1     READMR RDATA,,SEPCSS  CHECK CONTROL STORE SECDED ERRORS
          LDM    RDATA+2
          SHN    10
          ADM    RDATA+1
          LPC    0#5858      EXTRACT BITS 17, 19, 20, 9, 11, 12
          LJM    CCUX        RETURN
 CMH      SPACE  4,10
**        CMH - CHECK FOR MICROHALT (CONTROL STORE ADDRESSES 141 - 158).
*
*         EXIT   (A) = 0, IF MICROHALT.
*                    = 1, IF NOT MICROHALT.


 CMH      SUBR               ENTRY/EXIT
          LDML   CSA2        CHECK MICROHALT (CONTROL STORE ADDRESSES 141 - 158)
          SBK    0#141
          MJN    CMH1        IF CONTROL STORE ADDRESS BELOW HALT RANGE
          SBK    0#158+1-0#141
          PJN    CMH1        IF CONTROL STORE ADDRESS ABOVE HALT RANGE
          LDN    0           SET MICROHALT STATUS
          UJN    CMHX        RETURN

 CMH1     LDN    1           SET NO MICROHALT STATUS
          UJN    CMHX        RETURN
 HPR      SPACE  4,10
**        HPR - HALT PROCESSOR.
*
*         EXIT   TO *DCE* IF TIMED OUT TRYING TO HALT PROCESSOR.
*                (SUMS) = UPDATED (POST-HALT) SUMMARY STATUS.
*
*         CALLS  RMR, TIM.
*
*         MACROS FUNCMR.


 HPR      SUBR               ENTRY/EXIT
          FUNCMR ,MRHP       STOP PROCESSOR
          LDN    SSMR
          STD    RN

*         WAIT UP TO 500 MILLISECONDS FOR CPU TO HALT.

          LDN    0           RESET TIMER
          STML   ACTB1+2
          STML   TFLG
          STM    HPRA
 HPR1     LDD    EC          RECHECK SUMMARY STATUS
          RJM    RMR
          STM    SUMS
          LPN    0#8
          NJN    HPRX        IF PROCESSOR HALTED
          RJM    TIM         PROCESS TIMED EVENTS
          LDM    TFLG
          ZJN    HPR1        IF 100 MILLISECONDS NOT ELAPSED YET
          LDN    0
          STM    TFLG
          AOM    HPRA        ADVANCE COUNTER
          LMN    5
          NJN    HPR1        IF NOT 500 MILLISECONDS

*         SET UP SCRATCH BUFFER CONTROL WORD.
*
*         DFT ANALYSIS - ANALYSIS = CPU DEAD - HALT TIMED OUT.
*         DFT ANALYSIS - DFT ACTION = DISABLE CPU.
*         DFT ANALYSIS - ERROR PRIORITY = UNCORRECTED ERROR.
*         DFT ANALYSIS - FLAGS = LOG (CONSOLE), LOG (OS).

          SETDAC (DDDC)
          SETDAN (EPUN,DADTO)
          SETFLG (BC.CL,BC.FL)
          LJM    DCE         PROCESS DEAD CPU

 HPRA     BSS    1
 PCS      SPACE  4,10
**        PCS - PACK CONTROL STORE ADDRESSES.
*
*         EXIT   (CSA0) = SLOT 0 CONTROL STORE ADDRESS.
*                (CSA1) = SLOT 1 CONTROL STORE ADDRESS.
*                (CSA2) = SLOT 2 CONTROL STORE ADDRESS.
*
*         MACROS READMR.


 PCS      SUBR               ENTRY/EXIT
          READMR RDATA,,S0PCSA  READ AND SAVE CONTROL STORE ADDRESSES
          LDM    RDATA+2     PACK SLOT 0 ADDRESS
          SHN    10
          ADM    RDATA+3
          STML   CSA0
          LDM    RDATA+4     PACK SLOT 1 ADDRESS
          SHN    10
          ADM    RDATA+5
          STML   CSA1
          LDM    RDATA+6     PACK SLOT 2 ADDRESS
          SHN    10
          ADM    RDATA+7
          STML   CSA2
          LJM    PCSX        RETURN
 PKR      SPACE  4,10
**        PKR - PACK REGISTER.
*
*         ENTRY  (A) = ADDRESS TO STORE PACKED REGISTER.
*                (RDATA - RDATA+7) = REGISTER CONTENTS.
*
*         EXIT   ((A) - (A)+3) = PACKED REGISTER.
*
*         USES   T0.


 PKR      SUBR               ENTRY/EXIT
          STD    T0          SAVE DESTINATION ADDRESS
          LDM    RDATA       PACK BYTES 0 - 1 INTO FIRST PP WORD
          SHN    10
          ADM    RDATA+1
          STIL   T0
          AOD    T0
          LDM    RDATA+2     PACK BYTES 2 - 3 INTO NEXT PP WORD
          SHN    10
          ADM    RDATA+3
          STIL   T0
          AOD    T0
          LDM    RDATA+4     PACK BYTES 4 - 5 INTO NEXT PP WORD
          SHN    10
          ADM    RDATA+5
          STIL   T0
          AOD    T0
          LDM    RDATA+6     PACK BYTES 6 - 7 INTO NEXT PP WORD
          SHN    10
          ADM    RDATA+7
          STIL   T0
          UJN    PKRX        RETURN
 REL      SPACE  4,10
**        REL - READ ERROR LOG REGISTERS.
*
*         EXIT   (PUEL - PUEL+7) = UNCORRECTED ERROR LOG (PAIR 0#880/0#881).
*                (PFCL - PFCL+7) = FIRST/CORRECTED ERROR LOG (PAIR 0#890/0#891).
*
*         CALLS  PKR.
*
*         MACROS READMR.


 REL      SUBR               ENTRY/EXIT
          READMR RDATA,,S0PUEL  READ UNCORRECTED ERROR LOG (FIRST HALF)
          LDC    PUEL        PACK INTO *PUEL - PUEL+3*
          RJM    PKR
          READMR RDATA,,S0PUEL+1  READ UNCORRECTED ERROR LOG (SECOND HALF)
          LDC    PUEL+4      PACK INTO *PUEL+4 - PUEL+7*
          RJM    PKR
          READMR RDATA,,S0PFCL  READ FIRST/CORRECTED ERROR LOG (FIRST HALF)
          LDC    PFCL        PACK INTO *PFCL - PFCL+3*
          RJM    PKR
          READMR RDATA,,S0PFCL+1  READ FIRST/CORRECTED ERROR LOG (SECOND HALF)
          LDC    PFCL+4      PACK INTO *PFCL+4 - PFCL+7*
          RJM    PKR
          LJM    RELX        RETURN
 SCL      SPACE  4,10
**        SCL - SET CORRECTED LIST TO BE LOGGED.
*
*         CALLS  BRL.


 SCL      SUBR               ENTRY/EXIT
          LDM    CPUH        CHECK CPU ORDINAL
          NJN    SCL1        IF CPU-1
          LDM    CP0C        USE CPU-0 CORRECTED REGISTER LIST
          UJN    SCL2        CONTINUE

 SCL1     LDM    CP1C        USE CPU-1 CORRECTED REGISTER LIST
 SCL2     RJM    BRL
          UJN    SCLX        RETURN
 SML      SPACE  4,10
**        SML - SET PAGE MAP REGISTER LIST.
*
*         EXIT   REGISTER LIST BUILT WITH MEMORY, PAGE MAP, CPU SUBLISTS.
*                (EI) = (PMEI ).
*                (ET) = *DFTPMID*.
*
*         CALLS  BRL.
*
*         NOTE   THIS ASSUMES THAT CORRECTED AND UNCORRECTED LISTS MATCH.


 SML      SUBR               ENTRY/EXIT
          LDN    CMID        SET MEMORY REGISTERS TO LOG
          STD    ET
          LDC    MPMD0
          RJM    BRL
          LDN    DFTPMID     SET PAGE MAP *DEC* REGISTERS TO LOG
          STD    ET
          LDC    PD0
          RJM    BRL
          LDC    PM0         SET PAGE MAP REGISTERS TO LOG
          RJM    BRL
          LDN    PROCID      SET PROCESSOR REGISTERS TO LOG
          STD    ET
          LDC    PPM0
          RJM    BRL
          LDN    DFTPMID     RESTORE (ET)
          STD    ET
          LDM    PMEI        SET PAGE MAP ELEMENT INDEX
          STD    EI
          UJN    SMLX        RETURN
 SUL      SPACE  4,10
**        SUL - SET UNCORRECTED LIST TO BE LOGGED.
*
*         CALLS  BRL.


 SUL      SUBR               ENTRY/EXIT
          LDM    CPUH        CHECK CPU ORDINAL
          NJN    SUL1        IF CPU-1
          LDM    CP0U        USE CPU-0 UNCORRECTED REGISTER LIST
          UJN    SUL2        CONTINUE

 SUL1     LDM    CP1U        USE CPU-1 UNCORRECTED REGISTER LIST
 SUL2     RJM    BRL
          UJN    SULX        RETURN
 COMMON   SPACE  4,10
*         COMMON DECKS.


 QUAL$    EQU    0           DEFINE UNQUALIFIED COMMON DECK
*COPY CTP$DFT_START_MICROCODE
*COPY CTP$DFT_SAVE_CONTROL_STORE
*COPY CTP$DFT_CHECK_DEGRADABLE_CPU
          OVERFLOW  10000    CHECK FOR OVERFLOW
          OVERLAY  (ANALYZE IOU ERROR)
 AIE      SPACE  4,10
**        AIE - ANALYZE IOU ERROR.
*
*         ENTRY  SUMMARY STATUS INDICATES IOU ERROR.
*                (EC) = CONNECT CODE.
*                (ET) = *IOUID*.
*                (SUMS) = SUMMARY STATUS.


          ROUTINE  AIE

          LDN    0           SET NO ERROR FLAG FALSE
          STM    NERR
          LDN    BC          CLEAR SCRATCH BUFFER
          RJM    CLR
          CALL   CFF         CHECK FOR FREEZE
          LDM    RTP2
          ZJN    AIE0.5      IF NOT TO IGNORE ERROR
          LDN    0
          STM    DFTA        NO ACTION
          STM    REGI        RESET REGISTER LIST INDEX
          UJP    AIEX

 AIE0.5   LDM    SUMS        CHECK TYPE OF ERROR
          SHN    21-SSUE
          PJN    PCE         IF CORRECTED ERROR
          LJM    PUE         PROCESS UNCORRECTED ERROR

*         COMMON EXIT FROM CORRECTED/UNCORRECTED ERRORS.

 AIE1     CALL   LOG         LOG ERRORS
          LJM    AIEX        RETURN
 PCE      SPACE  4,10
**        PCE - PROCESS CORRECTED ERROR.
*
*         ENTRY  VIA *LJM*.
*
*         EXIT   TO *AIE1*.
*
*         CALLS  BRL, *RMR*.


 PCE      BSS    0           ENTRY
          LDM    IO0C
          RJM    BRL         BUILD REGISTER LIST FOR CORRECTED IOU ERROR
          CALL   RMR         READ MAINTENANCE REGISTERS

*         SET UP SCRATCH BUFFER CONTROL WORD.
*
*         DFT ANALYSIS - ANALYSIS = CORRECTED IOU ERROR.
*         DFT ANALYSIS - DFT ACTION = CLEAR ERROR.
*         DFT ANALYSIS - ERROR PRIORITY = CORRECTED ERROR.
*         DFT ANALYSIS - FLAGS = LOG (OS).

          SETDAC DDCL
          SETDAN (EPCO,DACIE)
          SETFLG (BC.FL)
          LJM    AIE1        RETURN
 PUE      SPACE  4,10
**        PUE - PROCESS UNCORRECTED ERROR.
*
*         ENTRY  VIA *LJM*.
*
*         EXIT   TO *AIE1*.
*
*         CALLS  BRL, CCE, CFE, CPH, *RMR*.


 PUE      BSS    0           ENTRY
          LDM    IO0U
          RJM    BRL         BUILD UNCORRECTED ERROR REGISTER LIST
          CALL   RMR         READ MAINTENANCE REGISTERS
          LDM    SUMS        CHECK TYPE OF ERROR
          SHN    21-SSPH
          PJP    PUE3        IF NOT PP HALT
          RJM    CPH         CHECK PP HALT
          ZJP    PUE3        IF NOT PP HALT IN *PFS* REGISTERS

*         SET UP SCRATCH BUFFER CONTROL WORD.
*
*         DFT ANALYSIS - ANALYSIS = UNCORRECTED IOU ERROR.
*         DFT ANALYSIS - DFT ACTION = CLEAR ERROR.
*         DFT ANALYSIS - ERROR PRIORITY = UNCORRECTED ERROR.
*         DFT ANALYSIS - FLAGS = LOG (CONSOLE), LOG (OS), VALID 180.
*         DFT ANALYSIS - OS ACTION = FATAL IOU ERROR.
*                                  = SYSTEM STEP (VERSION 4).

          SETDAC DDCL
          SETDAN (EPUN,DAUIE)
          SETFLG (BC.CL,BC.FL,BC.FV8)
          SETOSA OSVEI,OSSS

          LDN    D8TY
          RJM    IIB
          CRDL   CM
          LDDL   CM+3
          LPC    0#3F
          SBN    2
          MJN    PUE2        IF DFT LEVEL GREATER THAN OS LEVEL
          SETOSA OSVEI,OSHGP HUNG PP OS ACTION

 PUE2     LJM    PUEX        RETURN

 PUE3     RJM    CFE         CHECK FOR FATAL IOU ERROR
          ZJP    PUE5        IF NOT FATAL IOU ERROR

*         SET UP SCRATCH BUFFER CONTROL WORD.
*
*         DFT ANALYSIS - ANALYSIS = FATAL IOU ERROR.
*         DFT ANALYSIS - CLEAR ERROR.
*         DFT ANALYSIS - ERROR PRIORITY = UNCORRECTED ERROR.
*         DFT ANALYSIS - FLAGS = LOG (CONSOLE), LOG (OS), VALID 180.
*         DFT ANALYSIS - OS ACTION = FATAL IOU ERROR.
*                                  = SYSTEM STEP (VERSION 4).

 PUE4     SETDAC DDCL
          SETDAN (EPUN,DAFI)
          SETFLG (BC.CL,BC.FL,BC.FV8)
          SETOSA OSFIE,OSSS
 PUEX     LJM    AIE1        RETURN

 PUE5     RJM    CCE         CHECK FOR CHANNEL ERROR
          ZJP    PUE4        IF NOT CHANNEL DEFAULT IS FATAL

*         SET UP SCRATCH BUFFER CONTROL WORD.
*
*         DFT ANALYSIS - ANALYSIS = CHANNEL ERROR.
*         DFT ANALYSIS - DFT ACTION = CLEAR ERROR.
*         DFT ANALYSIS - ERROR PRIORITY = CORRECTED ERROR.
*         DFT ANALYSIS - FLAGS = LOG (OS)

          SETDAC DDCL
          SETDAN (EPCO,DACHE)
          SETFLG (BC.FL)
          UJN    PUEX        RETURN
 CCE      SPACE  4,10
**        CCE - CHECK CHANNEL ERROR.
*
*         EXIT   (A) <> 0 CHANNEL ERROR FOUND.
*                (A) = 0 CHANNEL ERROR NOT FOUND.
*


 CCE0     LDN    0

 CCE      SUBR               ENTRY/EXIT
          LDN    0           INITIALIZE REGISTER LOOP
          STD    T1
 CCE1     LDD    T1          READ NEXT CHANNEL FAULT STATUS REGISTER (CLUSTER 0)
          ADC    S0ICF0
          RJM    FMB         FIND REGISTER IN BUFFER
          CRDL   W0
          LDDL   W0
          LPC    0#0FFF
          NJP    CCEX        IF ERROR FOUND BITS 4-15
          LDDL   W1
          LPC    0#FFF
          NJP    CCEX        IF ERROR FOUND BITS 20-31
          LDDL   W2
          LPC    0#ACFE
          NJP    CCEX        IF ERROR FOUND BITS  32,34-37,40-46
          AOD    T1          ADVANCE TO NEXT REGISTER
          LMN    3
          NJN    CCE1
          LDM    CLST2       GET MULTIPLE CLUSTERS FLAG
          ZJP    CCE0        IF ONLY CLUSTER 0
          LDN    0           INITIALIZE REGISTER LOOP
          STD    T1
 CCE2     LDD    T1          READ NEXT CHANNEL FAULT STATUS REGISTER (CLUSTER 2)
          ADC    S0ICF2
          RJM    FMB         FIND REGISTER IN BUFFER
          CRDL   W0
          LDDL   W0
          LPC    0#0FFF
          NJP    CCEX        IF ERROR FOUND BITS 4-15
          LDDL   W1
          LPC    0#FFF
          NJP    CCEX        IF ERROR FOUND BITS 20-31
          LDDL   W2
          LPC    0#ACFE
          NJP    CCEX        IF ERROR FOUND BITS  32,34-37,40-46
          AOD    T1
          LMN    3
          NJN    CCE2        IF MORE TO CHECK
          LJM    CCEX        RETURN WITH NO ERROR INDICATION
 CFE      SPACE  4,10
**        CFE - CHECK FOR FATAL PP ERROR.
*
*         EXIT   (A) <> 0 IF FATAL PP ERROR FOUND.
*                (A) = 0 IF FATAL PP ERROR NOT FOUND.


 CFE0     LDN    0

 CFE      SUBR               ENTRY/EXIT
          LDC    S0IBF0      READ BUS ARBITER FAULT STATUS REGISTER (CLUSTER 0)
          RJM    FMB         FIND REGISTER IN BUFFER
          CRDL   W0
          LDDL   W0
          LPC    0#58        BITS 9,11,12
          NJN    CFEX        IF ERROR BITS SET
          LDDL   W1
          LPC    0#58        BITS 25,27,28
          NJN    CFEX        IF ERROR BITS SET
          LDM    CLST2       MULTIPLE CLUSTERS FLAG
          ZJN    CFE0        IF ONLY CLUSTER 0
          LDC    S0IBF2      READ BUS ARBITER FAULT STATUS REGISTER (CLUSTER 2)
          RJM    FMB         FIND REGISTER IN BUFFER
          CRDL   W0
          LDDL   W0
          LPC    0#58        BITS 9,11,12
          NJN    CFEX        IF ERROR BITS SET
          LDDL   W1
          LPC    0#58        BITS 25,27,28
          LJM    CFEX        RETURN WITH ERROR CONDITION IN (A)
 CPH      SPACE  4,10
**        CPH - CHECK FOR PP HALT.
*
*         EXIT   (A) <> 0 IF PP HALT FOUND.
*                (A) = 0 IF PP HALT NOT FOUND.


 CPH0     LDN    0           SET UP FOR NOT FOUND CONDITION

 CPH      SUBR               ENTRY/EXIT
          LDN    0           INITIALIZE REGISTER LOOP
          STD    T1
 CPH1     LDD    T1          READ NEXT FAULT STATUS REGISTER
          ADC    S0IFS0
          RJM    FMB         FIND REGISTER IN BUFFER
          CRDL   W0
          LDDL   W2          GET TO DUE, PP HALT BITS
          LPC    0#A000
          NJP    CPHX        IF PP HALTED
          AOD    T1          ADVANCE TO NEXT FAULT STATUS REGISTER
          LMN    5
          NJN    CPH1        IF MORE REGISTERS TO CHECK
          LDM    CLST2       GET MULTIPLE CLUSTERS FLAG
          ZJP    CPH0        IF NOT MULTIPLE CLUSTERS
          LDN    0           INITIALIZE REGISTER LOOP
          STD    T1
 CPH2     LDD    T1          READ NEXT FAULT STATUS REGISTER
          ADC    S0IFS2
          RJM    FMB         FIND REGISTER IN BUFFER
          CRDL   W0
          LDDL   W2          GET TO DUE, PP HALT BITS
          LPC    0#A000
          NJP    CPHX        IF PP HALTED
          AOD    T1
          LMN    5
          NJN    CPH2        IF MORE REGISTERS TO CHECK
          UJP    CPH0        RETURN

          OVERFLOW  10000    CHECK FOR OVERFLOW
          OVERLAY  (ANALYZE MEMORY ERROR)
 AME      SPACE  4,10
**        AME - ANALYZE MEMORY ERROR.
*
*         ENTRY  SUMMARY STATUS INDICATES MEMORY ERROR.
*                (EC) = CONNECT CODE.
*                (ET) = *CMID*.
*                (SUMS) = SUMMARY STATUS.
*
*         CALLS  CLR, GMI, PCE, PUE, *CFF*, *LOG*.


          ROUTINE  AME

          LDN    0           SET NO ERROR FLAG FALSE
          STM    NERR
          STM    RLST
          STM    SBER
          STM    SBER+1
          LDN    BC          CLEAR SCRATCH BUFFER
          RJM    CLR
          CALL   CFF         CHECK FOR FREEZE
          LDM    RTP2
          ZJN    AME0        IF NOT TO IGNORE ERROR
          LDN    0
          STM    DFTA        NO ACTION
          STM    REGI        RESET REGISTER LIST
          UJP    AMEX

 AME0     LDM    SUMS        CHECK TYPE OF ERROR
          SHN    21-SSUE
          MJP    PUE         IF UNCORRECTED ERROR
          SHN    1
          MJP    PCE         IF CORRECTED ERROR

*         CAN GET HERE IF A PAGE MAP ERROR EXISTS. IF IT DOES PASS CONTROL TO
*         ANALYZE PROCESSOR ERRORS, AND DONT DO ANY ACTIONS ON THIS ERROR HERE.

          LDN    0           SET UP NULL ACTION LIST
          STM    DFTA
 AME1     LJM    AMEX        RETURN
 CMRLP    SPACE  4,10
**        CORRECTED MEMORY REGISTER LIST POINTERS.


 CMRLP    CON    MC00        BOARD 0 BANK 0
          CON    MC01        BOARD 0 BANK 1
          CON    MC02        BOARD 0 BANK 2
          CON    MC03        BOARD 0 BANK 3

          CON    MC10        BOARD 1 BANK 0
          CON    MC11        BOARD 1 BANK 1
          CON    MC12        BOARD 1 BANK 2
          CON    MC13        BOARD 1 BANK 3

          CON    MC20        BOARD 2 BANK 0
          CON    MC21        BOARD 2 BANK 1
          CON    MC22        BOARD 2 BANK 2
          CON    MC23        BOARD 2 BANK 3

          CON    MC30        BOARD 3 BANK 0
          CON    MC31        BOARD 3 BANK 1
          CON    MC32        BOARD 3 BANK 2
          CON    MC33        BOARD 3 BANK 3

          ERRNZ  *-CMRLP-20  TABLE SIZE INCORRECT
 UMBE     SPACE  4,10
**        UNCORRECTED REGISTER LIST FOR MEMORY BOARD ERRORS.

 UMBE     CON    MUB0        BOARD 0
          CON    MUB1        BOARD 1
          CON    MUB2        BOARD 2
          CON    MUB3        BOARD 3

          ERRNZ  *-UMBE-4   TABLE SIZE INCORRECT
 UMRLP    SPACE  4,10
**        UNCORRECTED MEMORY REGISTER LIST POINTERS.


 UMRLP    CON    MU00        BOARD 0 BANK 0
          CON    MU01        BOARD 0 BANK 1
          CON    MU02        BOARD 0 BANK 2
          CON    MU03        BOARD 0 BANK 3

          CON    MU10        BOARD 1 BANK 0
          CON    MU11        BOARD 1 BANK 1
          CON    MU12        BOARD 1 BANK 2
          CON    MU13        BOARD 1 BANK 3

          CON    MU20        BOARD 2 BANK 0
          CON    MU21        BOARD 2 BANK 1
          CON    MU22        BOARD 2 BANK 2
          CON    MU23        BOARD 2 BANK 3

          CON    MU30        BOARD 3 BANK 0
          CON    MU31        BOARD 3 BANK 1
          CON    MU32        BOARD 3 BANK 2
          CON    MU33        BOARD 3 BANK 3

          ERRNZ  *-UMRLP-20 TABLE SIZE INCORRECT
 CBE      SPACE  4,10
**        CBE - CHECK FOR BANK ERROR.
*
*         ENTRY  (BRDI) = BOARD BEING CHECKED.
*                (BKER) = 0.
*                (A) = 1 IF PROCESSING UNCORRECTED ERROR.
*                (A) = 0 IF PROCESSING CORRECTED ERROR.
*
*         EXIT   (A) = (BKER) = 1 IF BANK ERROR(S) DETECTED.
*
*         USES   T1 - T4.


 CBE      SUBR               ENTRY/EXIT
          STM    CBEA
          LDN    0
          STM    BKER        RESET BANK ERROR FOUND
          LDM    BRDI        CALCULATE REGISTER TO BE CHECKED
          SHN    2
          ADM    BNKI
          STD    T1
          LDM    CBEA        SET CORRECTED/UNCORRECTED
          STD    T2
          LDM    CBED,T2     GET CORRECT REGISTER BASE FOR EITHER CORR OR UNCORR
          ADD    T1          ADD IN BANK AND BOARD ADJUSTMENT
          STD    RN
          READMR RDATA       CHECK FOR BANK ERROR (BIT 16)
          LDML   RDATA+2
          SHN    21-7
          PJP    CBE2        IF NO BANK ERROR
          LDM    BRDI        GET BOARD NUMBER
          SHN    2           MULTIPLY BY 4 FOR PROPER BOARD OFFSET
          ADM    BNKI        GET BANK INDEX
          STD    T4          ADD BANK INDEX WITHIN BOARD INDEX
          LDM    CBEA        FLAG FOR UNCORR OR CORR ERROR PROCESSING
          STD    T2

*         BUILD COMMON REGISTER LIST.

          LDM    CBEC,T2     GET CORRECT COMMON REGISTER LIST
          STD    T3
          LDI    T3
          RJM    BRL         BUILD REGISTER LIST

*         BUILD REGISTER LIST FOR BANK AFFECTED.

          LDM    CBEB,T2     GET CORRECT LIST HEAD
          RAD    T4          UPDATE WITH UNCORRECTED/CORRECTED LIST HEAD
          LDI    T4
          RJM    BRL         BUILD BANK REGISTER LIST WITHIN THIS BOARD
          AOM    BKER        SET BANK ERROR TRUE
          AOM    MEER        SET ANY MEMORY ERROR FLAG
          LDM    BNKI        SAVE BANK WITH ERROR
          SBM    DEGR        CONVERT BANKS 2,3 TO 0,1 FOR NUMBERING SCHEME
          STM    BKNO
 CBE2     LDM    BKER
          LJM    CBEX        RETURN

 CBEA     BSS    1           CORRECTED/UNCORRECTED FLAG
 CBEB     CON    CMRLP       CORRECTED REGISTER LIST
          CON    UMRLP       UNCORRECTED REGISTER LIST
 CBEC     CON    ME0C        COMMON REGISTERS FOR CORRECTED ERROR
          CON    ME0U        COMMON REGISTERS FOR UNCORRECTED ERROR
 CBED     CON    S0MCD       REGISTER BASE FOR CORRECTED ERROR
          CON    S0MUD       REGISTER BASE FOR UNCORRECTED ERROR
 CBK      SPACE  4,10
**        CBK - PROCESS CORRECTED BANK ERROR.
*
*         ENTRY  VIA *LJM*.
*
*         EXIT   TO *PCE2*.
*
*         CALLS  FMA, GSC, *SME*.


 CBK      BSS    0           ENTRY

*         SET UP SCRATCH BUFFER CONTROL WORD.
*
*         DFT ANALYSIS - ANALYSIS = CORRECTED MEMORY ERROR.
*         DFT ANALYSIS - DFT ACTION = CLEAR ERROR.
*         DFT ANALYSIS - ERROR PRIORITY = CORRECTED ERROR.
*         DFT ANALYSIS - FLAGS = LOG (OS).

          SETDAC DDCL
          SETDAN (EPCO,DACME)
          SETFLG (BC.FL)

*         REWRITE MEMORY WITH CORRECTED FAILURE.

          RJM    GSC         GET SYNDROME CODE
          RJM    FMA         FORM MEMORY ADDRESS
          CALL   SME         SERVICE MEMORY ERROR
          LJM    PCE2        RETURN
 CBS      SPACE  4,10
**        CBS - CHECK FOR BIT SET IN REGISTERS.
*
*         ENTRY  (A) = BASE REGISTER TO CHECK.
*
*         EXIT   (A) = NONZERO, IF BIT(S) SET IN REGISTER (A) OR (A)+4.


 CBS      SUBR               ENTRY/EXIT
          STD    RN          CHECK BASE REGISTER
          READMR RDATA
          LDML   RDATA       CHECK FOR ANY BIT(S) SET
          ADML   RDATA+1
          ADML   RDATA+2
          ADML   RDATA+3
          ADML   RDATA+4
          ADML   RDATA+5
          ADML   RDATA+6
          ADML   RDATA+7
          NJN    CBSX        IF BIT(S) SET
          LDN    4           CHECK BASE+4
          RAD    RN
          READMR RDATA
          LDML   RDATA       CHECK FOR ANY BIT(S) SET
          ADML   RDATA+1
          ADML   RDATA+2
          ADML   RDATA+3
          ADML   RDATA+4
          ADML   RDATA+5
          ADML   RDATA+6
          ADML   RDATA+7
          LJM    CBSX        RETURN WITH RESULT
 CIF      SPACE  4,10
**        CIF - CENTRAL MEMORY INTERFACE ERROR.
*
*         ENTRY  MAINTENANCE REGISTERS FOR ERROR READ INTO THE SCRATCH BUFFER.
*
*         EXIT   (A) = 0 IMPLIES NO ERROR.
*                (A) = 1 IMPLIES ERROR FOUND.
*
*         USES   CM.
*
*         MACROS READMR, SETDAC, SETDAN, SETFLG, SETOSA.
*
*         CALLS  FMB.


 CIF0     LDN    0           SET FOR NO ERROR FOUND

 CIF      SUBR               ENTRY/EXIT
          READMR RDATA,,S0MBA  CENTRAL MEMORY BUS ARBITRATOR
          LDM    RDATA
          SHN    12          POSITION TO LOGGED ERROR BIT
          PJP    CIF0        IF NOT LOGGED
          LDM    ME0U        UNCORRECTED COMMON REGISTERS
          RJM    BRL         BUILD REGISTER LIST

*         SET UP SCRATCH BUFFER CONTROL WROD.
*
*         DFT ANALYSIS - ANALYSIS = CENTRAL MEMORY INTERFACE ERROR.
*         DFT ANALYSIS - DFT ACTION = CLEAR ERROR.
*         DFT ANALYSIS - ERROR PRIORITY = UNCORRECTED ERROR.
*         DFT ANALYSIS - FLAGS = LOG (CONSOLE), LOG (OS), VALID 180.
*         DFT ANALYSIS - OS ACTION = UNCORRECTED MEMORY ERROR.
*                                  = NO OS ACTION (VERSION 4).

          SETDAC DDCL
          SETDAN (EPUN,DACMI)
          SETFLG (BC.CL,BC.FL,BC.FV8)
          SETOSA OSUCM,OSNA
          LDN    1
          LJM    CIFX        RETURN
 FMA      SPACE  4,10
**        FMA - FORM MEMORY ADDRESS.
*
*         ENTRY  (BRDI) = BOARD INDEX.
*                (BNKI) = BANK INDEX.
*
*         EXIT   (SBER - SBER+1) = ADDRESS OF ERROR -
*                (SBER) = BITS 18-26 FROM REGISTER D_X.
*                (SBER+1) = BITS 27-31 * 2**11
*                (SBER+1) = BITS 0-1 OF REGISTER E_X * 2**9
*                (SBER+1) = (BKNO) IN LEAST SIGNIFICANT BITS (BITS 0,1).
*                           OR IF DEGRADE BIT 0.
*
*         CALLS  FMB.


 FMA      SUBR               ENTRY/EXIT
          LDM    BRDI        READ FIRST REGISTER (E_X)
          SHN    2
          ADM    BNKI
          STD    T1          SAVE LOWER NIBBLE OF REGISTER NUMBER
          ADC    S0MBC       READ CORRECTED BANK CONTROL REGISTER
          RJM    FMB
          CRDL   CM          READ THE REGISTER FROM SCRATCH MRB
          LDDL   CM          EXTRACT BITS 0-1
          SHN    -16
          LPN    3
          SHN    11
          STML   SBER+1
          LDD    T1          GET PROPER (D_X) REGISTER
          ADC    S0MCD       READ CORRECTED BANK DATA AND CONTROL
          RJM    FMB
          CRDL   CM          READ D_X REGISTER FROM SCRATCH MRB
          LDDL   CM+1        EXTRACT BITS 27-31
          LPN    0#1F
          SHN    13
          RAML   SBER+1
          LDDL   CM+1        EXTRACT BITS 18-26
          SHN    -5
          LPC    0#1FF
          STML   SBER
          LDM    BKNO
          RAML   SBER+1      ADD IN BANK NUMBER
          LJM    FMAX        RETURN
 GSC      SPACE  4,10
**        GSC - GET SYNDROME CODE.
*
*         ENTRY  (BRDI) = BOARD INDEX.
*                (BNKI) = BANK INDEX.
*
*         EXIT   (SYCD) = SYNDROME CODE.
*
*         CALLS  FMB.


 GSC      SUBR               ENTRY/EXIT
          LDM    BRDI        BOARD INDEX
          SHN    2
          ADM    BNKI        BANK INDEX
          ADC    S0MCD       READ CORRECTED BANK DATA AND CONTROL
          RJM    FMB
          CRDL   CM          GET D_X REGISTER FROM SCRATCH MRB
          LDDL   CM
          SHN    -10
          STM    SYCD        SAVE SYNDROME CODE
          UJN    GSCX        RETURN
 PBD      SPACE  4,10
**        PBD - PROCESS BOARD ERROR.
*
*         ENTRY  VIA *LJM*.
*                (BRDI) = BOARD BEING CHECKED.
*
*         EXIT   TO *PUE3*.
*
*
*         USES   T3.


 PBD      BSS    0           ENTRY
          LDM    BRDI        BOARD INDEX
          ADC    S0MIB       SET INPUT BUFFER REGISTER
          RJM    CBS         CHECK FOR BIT(S) IN REGISTERS 9X AND 9X+4
          ZJP    PBDX        IF NO BITS SET
          LDM    ME0U        UNCORRECTED COMMON REGISTERS
          RJM    BRL         BUILD REGISTER LIST
          AOM    BDER        SET BOARD ERROR FLAG
          AOM    MEER        SET MEMORY ERROR OCCURRED FLAG
          LDM    BRDI        CURRENT BOARD INDEX
          ADC    UMBE        MEMORY BOARD REGISTER LIST
          STD    T3
          LDI    T3          GET LIST
          RJM    BRL         BUILD REGISTER LIST

*         SET UP SCRATCH BUFFER CONTROL WORD.
*
*         DFT ANALYSIS - ANALYSIS = UNCORRECTED MEMORY BOARD ERROR.
*         DFT ANALYSIS - DFT ACTION = CLEAR ERROR.
*         DFT ANALYSIS - ERROR PRIORITY = UNCORRECTED ERROR.
*         DFT ANALYSIS - FLAGS = LOG (CONSOLE), LOG (OS), VALID 180.
*         DFT ANALYSIS - OS ACTION = UNCORRECTED MEMORY ERROR.
*                                  = NO OS ACTION (VERSION 4).

          SETDAC DDCL
          SETDAN (EPUN,DAUMB)
          SETFLG (BC.CL,BC.FL,BC.FV8)
          SETOSA OSUCM,OSNA
          CALL   RMR         READ MAINTENANCE REGISTERS
          CALL   LOG         LOG THE ERROR
 PBDX     LJM    PUE3        RETURN
 PCE      SPACE  4,10
**        PCE - PROCESS CORRECTED ERROR.
*
*         ENTRY  VIA *LJM*.
*                (NBRDS) = BOARD CONFIGURATION.
*
*         EXIT   TO *AME1*.
*
*         CALLS  BRL, CBE, CBK, *RMR*.


 PCE      BSS    0           ENTRY
          LDN    0
          STM    BRDI        INITIALIZE BOARD INDEX
          LDM    SBNK        STARTING BANK
          STM    BNKI        INITIALIZE BANK INDEX
          AOM    RLST        SET CORRECTED ERROR FLAG
 PCE1     LDN    0
          STM    BKER        INITIALIZE BANK ERROR
*         LDN    0           SET FLAG FOR CORRECTED ERROR
          RJM    CBE         CHECK BANK ERROR
          ZJN    PCE2        IF NO BANK ERROR
          CALL   RMR         READ MAINTENANCE REGISTERS
          LJM    CBK         PROCESS CORRECTED BANK ERROR

*         *CBK* RETURNS HERE.

 PCE2     AOM    BNKI        INCREMENT BANK INDEX
          LMM    NBNK
          NJN    PCE1        IF MORE BANKS TO CHECK
          LDN    0
          STM    BNKI        RESET BANKS
          AOM    BRDI        BOARD INDEX
          LMM    NBRDS       NUMBER OF BOARDS INSTALLED
          NJN    PCE1        IF MORE BOARDS
          LDM    MEER        GET MEMORY ERROR OCCURRED FLAG
          NJP    AME1        IF AN ERROR WAS FOUND
          LDM    ME0C        CORRECTED REGISTER LIST
          RJM    BRL         BUILD REGISTER LIST
          CALL   RMR         READ MAINTENANCE REGISTERS
          CALL   LOG         LOG ERROR
          LJM    AME1        RETURN
 PUE      SPACE  4,10
**        PUE - PROCESS UNCORRECTED ERROR.
*
*         ENTRY  VIA *LJM*.
*                (NBRDS) = BOARD CONFIGURATION.
*
*         EXIT   TO *AME1*.
*
*         CALLS  BRL, CBE, CIF, PBD, UBK, *RMR*.


 PUE      BSS    0           ENTRY
          LDN    0
          STM    MEER        INITIALIZE GLOBAL MEMORY ERROR FLAG FALSE
          STM    BRDI        BOARD INDEX
          STM    BNKI        BANK INDEX
 PUE1     LDN    0
          STM    BDER        BOARD ERROR = FALSE
          STM    BKER        BANK ERROR = FALSE
          LDN    1           SET FLAG FOR UNCORRECTED ERROR
          RJM    CBE         CHECK BANK ERROR
          ZJN    PUE2        IF NO BANK ERROR
          CALL   RMR         READ MAINTENANCE REGISTERS
          LJM    UBK         PROCESS UNCORRECTED MEMORY ERROR

*         *UBK* RETURNS HERE.

 PUE2     AOM    BNKI        INCREMENT BANK INDEX
          LMM    NBNK
          NJN    PUE1        IF MORE BANKS
          LDN    0
          STM    BNKI
          LDM    BKER        GET BANK ERROR FOUND
          NJN    PUE3        IF BANK ERROR
          LJM    PBD         CHECK BOARD ERROR

*         *PBD* RETURNS HERE.

 PUE3     LDN    0
          STM    BNKI        RESET BANK INDEX
          AOM    BRDI        INCREMENT BOARD INDEX
          LMM    NBRDS
          NJP    PUE1        IF MORE BOARDS
          LDM    MEER        ANY MEMORY ERROR FOUND
          NJP    PUE5        IF ERROR ISOLATED
          RJM    CIF         CHECK CENTRAL MEMORY INTERFACE
          NJP    PUE4        IF ERROR FOUND
          LDM    ME0U        UNCORRECTED COMMON REGISTER LIST
          RJM    BRL         BUILD REGISTER LIST

*         SET UP SCRATCH BUFFER CONTROL WORD.
*
*         DFT ANALYSIS - ANALYSIS = UNCORRECTED MEMORY ERROR.
*         DFT ANALYSIS - DFT ACTION = CLEAR ERROR.
*         DFT ANALYSIS - ERROR PRIORITY = UNCORRECTED ERROR.
*         DFT ANALYSIS - FLAGS = LOG (CONSOLE), LOG (OS), VALID 180.
*         DFT ANALYSIS - OS ACTION = UNCORRECTED MEMORY ERROR.
*                                  = NO OS ACTION (VERSION 4).

          SETDAC DDCL
          SETDAN (EPUN,DAUME)
          SETFLG (BC.CL,BC.FL,BC.FV8)
          SETOSA OSUCM,OSNA
 PUE4     CALL   RMR         READ MAINTENANCE REGISTERS
          CALL   LOG         LOG THE ERROR
 PUE5     LJM    AME1        RETURN
 REW      SPACE  4,10
**        REW - REWRITE AREA WITH SINGLE BIT ERROR.
*
*         THE S0/S0E DOES NOT IDENTIFY THE PRECISE WORD WITH AN ERROR,
*         SO 512 WORDS MUST BE REWRITTEN.  CLEVER.
*
*         ENTRY  (SBER - SBER+1) = ADDRESS BASE.


          ROUTINE  REW

          RJM    DBC         DISABLE BOUNDS CHECKING
          LDML   SBER        SET UP R-REGISTER
          STDL   W2
          LDML   SBER+1
          STDL   W3
          RJM    STA         CALCULATE R-REGISTER
          STDL   W0
          SRD    W0+1
          ADC    1000        CALCULATE LWA+1 TO PROCESS
          STDL   W0+3
          READMR RDATA,,ECMR  CHECK DEGRADE MODE
          LDML   RDATA
          LPN    6
          ZJN    REW1        IF MEMORY NOT DEGRADED
          LCN    2
 REW1     ADN    4           SET ADDRESS INCREMENT
          STD    T0
 REW2     LDN    CM          CLEAR (CM - CM+3)
          RJM    CLR
          LDDL   W0          REWRITE NEXT WORD
          ADC    RR
          RDSL   CM
          LDD    T0          ADVANCE ADDRESS
          RADL   W0
          SBDL   W0+3
          MJN    REW2        IF MORE WORDS TO PROCESS
          RJM    EBC         ENABLE BOUNDS CHECKING
          LJM    REWX        RETURN
 UBK      SPACE  4,10
**        UBK - PROCESS UNCORRECTED BANK ERROR.
*
*         ENTRY  VIA *LJM*.
*
*         EXIT   TO *PUE2*.
*                (BDER) = 0.


 UBK      BSS    0           ENTRY
          LDN    0           CLEAR BOARD ERRORS
          STM    BDER

*         SET UP SCRATCH BUFFER CONTROL WORD.
*
*         DFT ANALYSIS - ANALYSIS = UNCORRECTED MEMORY ERROR.
*         DFT ANALYSIS - DFT ACTION = CLEAR ERROR.
*         DFT ANALYSIS - ERROR PRIORITY = UNCORRECTED ERROR.
*         DFT ANALYSIS - FLAGS = LOG (CONSOLE), LOG (OS), VALID 180.
*         DFT ANALYSIS - OS ACTION = UNCORRECTED MEMORY ERROR.
*                                  = NO OS ACTION (VERSION 4).

          SETDAC DDCL
          SETDAN (EPUN,DAUME)
          SETFLG (BC.CL,BC.FL,BC.FV8)
          SETOSA OSUCM,OSNA
          CALL   LOG         LOG THE ERROR
          LJM    PUE2        RETURN
*COPYC CTP$DFT_SERVICE_MEMORY_ERROR
          QUAL   *

          OVERFLOW  10000    CHECK FOR OVERFLOW
          OVERLAY  (GENERATE FAULT SYMPTOM CODE)
 OVERVIEW SPACE  4,10
***       FAULT SYMPTOM CODE OVERVIEW.
*
*         THIS OVERLAY EXAMINES THE MAINTENANCE REGISTERS ACCORDING TO AN
*         ALGORITHM DEVELOPED BY CANCDD AND PRODUCES A 12-CHARACTER FAULT
*         SYMPTOM CODE WITH THE FOLLOWING FORMAT:
*
*         *DEMMTRRBBNN *
*
*         D = CHARACTER *D* (TO SIGNIFY DFT-PRODUCED ANALYSIS.)
*         E = *C*/*D* FOR CPU 0/1, *I* FOR IOU, *M* FOR MEMORY, *P* FOR MAP.
*         MM = MODEL NUMBER OF ELEMENT WITH FAILURE (SEE NOTE IN *GFS*).
*         T = REGISTER TYPE (0 OR 8) OF FIRST REGISTER WITH FAILURE DATA.
*         RR = HEX NUMBER OF FIRST REGISTER FOUND WITH ERROR BIT(S) SET.
*         BB = DECIMAL NUMBER OF FIRST ERROR BIT (MSB = BIT 0, LSB = BIT 63).
*         NN = DECIMAL NUMBER OF REGISTERS WITH ERROR BIT(S) SET.
*
*         IF THE DFT ANALYSIS CODE IS AN ENVIRONMENT OR SHORT WARNING THE FAULT
*         SYMPTOM CODE PRODUCED IS:
*
*         *DEMMXXX*
*
*         WHERE XXX IS THE DFT ANALYSIS CODE.
 GSB      SPACE  4,10
**        GSB - GENERATE BLANK SYMPTOM CODE.
*
*         EXIT   FAULT SYMPTOM CODE IN SUPPORTIVE STATUS BUFFER ALL BLANKS.
*
*         USES   CM - CM+3, T1, W0 - W0+3.
*
*         CALLS  IDA.


          ROUTINE  GSB

          LDN    2           SET NUMBER OF CM WORDS TO READ/WRITE
          STD    T1
          LDN    SSBP        GET ADDRESS OF SCRATCH ENTRY
          RJM    IDA
          CRDL   CM
          LDN    3           SKIP HEADER WORDS
          RADL   CM
          LRD    CM+1
          ADC    RR
          CRDL   W0
          LDC    2R          SPACE FILL FIRST PART OF SYMPTOM CODE
          STDL   W0+2
          STDL   W0+3
          LDD    CM          REWRITE FIRST PART OF SYMPTOM CODE
          ADC    RR
          CWDL   W0
          LDC    2R          SPACE FILL SECOND PART OF SYMPTOM CODE
          STDL   W0
          STDL   W0+1
          LDD    CM          REWRITE SECOND PART OF SYMPTOM CODE
          ADC    RR+1
          CWDL   W0
          LJM    GSBX        RETURN
 GIE      SPACE  4,10
**        GIE - GENERATE INTERNAL ERROR FSC.
*
*         ENTRY  5XX AND 6XX CODES ARE HANDLED.


          ROUTINE GIE
          LDM    IOUM
          STD    MD
          LDC    2RDI        IOU ELEMENT IDENTIFIER
          RJM    WFC         WRITE FAULT SYMPTOM
          LJM    GIEX
 GSC      SPACE  4,10
**        GSC - GENERATE FAULT SYMPTOM CODE FOR CPU ERROR.
*
*         ENTRY  SCRATCH MRB CONTAINS LOGGED REGISTERS.


          ROUTINE  GSC

          LDDL   BC+BCDA     GET THE DFT ANALYSIS
          SHN    -BC.ANP
          SBN    EPEN
          MJN    GSC0        IF NOT ENVIRONMENT OR LONG WARN
          LDC    2RDC
          ADM    CPUO
          RJM    WFC         WRITE THE FAULT CODE
          LJM    GSCX

 GSC0     LDN    0           INITIALIZE VALUES
          STM    BITN        INITIALIZE BIT NUMBER OF FIRST ERROR
          STM    REGC        INITIALIZE NUMBER OF REGISTERS WITH ERROR(S)
          STM    REGN        INITIALIZE REGISTER NUMBER WITH FIRST ERROR

*         CHECK FIRST FAILURE CAPTURE REGISTERS (0#2890 - 0#2891).

          LDC    0#2890
          RJM    CAB         CHECK IF ANY ERROR BITS SET
          LDC    0#2891
          RJM    CAB         CHECK IF ANY ERROR BITS SET

*         CHECK ACCUMULATED ERROR REGISTERS (0#2880 - 0#2881).

          LDC    0#2880
          RJM    CAB         CHECK IF ANY ERROR BITS SET
          LDC    0#2881
          RJM    CAB         CHECK IF ANY ERROR BITS SET

*         CHECK DETAILED ERROR REGISTERS.
*         FOR S0, CHECK 0#2090 - 0#20AE.
*         FOR S0E, CHECK 0#2090 - 0#20A7.

          LDC    0#2090      INITIALIZE REGISTER LOOP
          STDL   W0
          LDM    S0EFLG      CHECK MAINFRAME TYPE
          ZJN    GSC1        IF NOT S0E
          LCN    0#20AE-0#20A7
 GSC1     ADC    0#20AE+1
          STDL   W1          SET LAST REGISTER TO SCAN
 GSC2     LDDL   W0          CHECK NEXT REGISTER
          RJM    CAB         CHECK IF ANY ERROR BITS SET
          AODL   W0          ADVANCE REGISTER NUMBER
          LMDL   W1
          NJN    GSC2        IF MORE REGISTERS TO CHECK

*         CHECK CONTROL STORE CORRECTED ERROR REGISTER (0#20C0).

          LDC    0#20C0
          RJM    CAB         CHECK IF ANY ERROR BITS SET

*         COMPLETE GENERATION OF FAULT SYMPTOM CODE.

          LDC    2RDC        SET FAULT SYMPTOM CODE PREFIX
          ADM    CPUO
          RJM    GFS         GENERATE FAULT SYMPTOM CODE
          LJM    GSCX        RETURN
 GSI      SPACE  4,10
**        GSI - GENERATE FAULT SYMPTOM CODE FOR IOU ERROR.
*
*         ENTRY  SCRATCH MRB CONTAINS LOGGED REGISTERS.


          ROUTINE  GSI

          LDDL   BC+BCDA
          SHN    -BC.ANP
          SBN    EPEN
          MJP    GSI0        IF NOT ENVIRONMENT ERROR
          LDC    2RDI
          RJM    WFC         WRITE FAULT CODE
          LJM    GSIX        RETURN

 GSI0     LDN    0           INITIALIZE VALUES
          STM    BITN        INITIALIZE BIT NUMBER OF FIRST ERROR
          STM    BUS0        CLEAR BIT 39 FLAG FOR REGISTERS 90 - 94
          STM    BUS2        CLEAR BIT 39 FLAG FOR REGISTERS A0 - A4
          STM    REGC        INITIALIZE NUMBER OF REGISTERS WITH ERROR(S)
          STM    REGN        INITIALIZE REGISTER NUMBER WITH FIRST ERROR

*         CHECK CLUSTER 0 PP ERROR REGISTERS (0#0090 - 0#0094).
*         IF BIT 32 OR 33 IS SET, REGISTER CONTENTS HAVE MEANING.
*         BIT 39 OF EACH REGISTER IS ALSO EXAMINED FOR LATER USE
*         BY BUS ARBITER ERROR REGISTER CHECKING.

          LDC    0#0090      INITIALIZE REGISTER LOOP
          STDL   W0
 GSI1     LDDL   W0          CHECK NEXT REGISTER
          STDL   RN
          RJM    GMB         READ REGISTER FROM SCRATCH MRB
          ZJN    GSI3        IF REGISTER NOT FOUND
          CRDL   CM
          LDDL   CM+2        CHECK BIT 39 STATUS
          LPC    0#0100      EXTRACT BIT 39 FOR BUS ARBITER CHECKING
          RAM    BUS0
          LDDL   CM+2        CHECK BITS 32 - 33
          LPC    0#C000
          ZJN    GSI3        IF NO ERRORS LOGGED
          LDN    0           SET REGISTER ALREADY READ
          RJM    CAB         CHECK IF ANY ERROR BITS SET
 GSI3     AODL   W0          ADVANCE REGISTER NUMBER
          LMC    0#0094+1
          NJN    GSI1        IF MORE REGISTERS TO CHECK

*         CHECK CLUSTER 0 CHANNEL ERROR REGISTERS (0#00B0 - 0#00B2).
*         ONLY BITS 4 - 15, 20 - 32, 34 - 37, 40 - 46 HAVE MEANING.

          LDC    0#00B0      INITIALIZE REGISTER LOOP
          STDL   W0
 GSI4     LDDL   W0          CHECK NEXT REGISTER
          STDL   RN
          RJM    GMB         READ REGISTER FROM SCRATCH MRB
          ZJN    GSI6        IF REGISTER NOT FOUND
          CRDL   CM
          LDDL   CM          PRESERVE BITS 4 - 15
          LPC    0#0FFF
          STDL   CM
          LDDL   CM+1        PRESERVE BITS 20 - 31
          LPC    0#0FFF
          STDL   CM+1
          LDDL   CM+2        PRESERVE BITS 32, 34 - 37, 40 - 46
          LPC    0#BCFE
          STDL   CM+2
          LDN    0
          STDL   CM+3
*         LDN    0           SET REGISTER ALREADY READ
          RJM    CAB         CHECK IF ANY ERROR BITS SET
 GSI6     AODL   W0          ADVANCE REGISTER NUMBER
          LMC    0#00B2+1
          NJN    GSI4        IF MORE REGISTERS TO CHECK

*         CHECK CLUSTER 2 PP ERROR REGISTERS (0#00A0 - 0#00A4).
*         IF BIT 32 OR 33 IS SET, REGISTER CONTENTS HAVE MEANING.

          LDC    0#00A0      INITIALIZE REGISTER LOOP
          STDL   W0
 GSI7     LDDL   W0          CHECK NEXT REGISTER
          STDL   RN
          RJM    GMB         READ REGISTER FROM SCRATCH MRB
          ZJN    GSI9        IF REGISTER NOT FOUND
          CRDL   CM
          LDDL   CM+2        CHECK BIT 39 STATUS
          LPC    0#0100      EXTRACT BIT 39 FOR BUS ARBITER CHECKING
          RAM    BUS2
          LDDL   CM+2        CHECK BITS 32 - 33
          LPC    0#C000
          ZJN    GSI9        IF NO ERRORS LOGGED
          LDN    0           SET REGISTER ALREADY READ
          RJM    CAB         CHECK IF ANY ERROR BITS SET
 GSI9     AODL   W0          ADVANCE REGISTER NUMBER
          LMC    0#00A4+1
          NJN    GSI7        IF MORE REGISTERS TO CHECK

*         CHECK CLUSTER 2 CHANNEL ERROR REGISTERS (0#00B8 - 0#00BA).
*         ONLY BITS 4 - 15, 20 - 32, 34 - 37, 40 - 46 HAVE MEANING.

          LDC    0#00B8      INITIALIZE REGISTER LOOP
          STDL   W0
 GSI10    LDDL   W0          CHECK NEXT REGISTER
          STDL   RN
          RJM    GMB         READ REGISTER FROM SCRATCH MRB
          ZJN    GSI11       IF REGISTER NOT FOUND
          CRDL   CM
          LDDL   CM          PRESERVE BITS 4 - 15
          LPC    0#0FFF
          STDL   CM
          LDDL   CM+1        PRESERVE BITS 20 - 31
          LPC    0#0FFF
          STDL   CM+1
          LDDL   CM+2        PRESERVE BITS 32, 34 - 37, 40 - 46
          LPC    0#BCFE
          STDL   CM+2
          LDN    0
          STDL   CM+3
*         LDN    0           SET REGISTER ALREADY READ
          RJM    CAB         CHECK IF ANY ERROR BITS SET
 GSI11    AODL   W0          ADVANCE REGISTER NUMBER
          LMC    0#00BA+1
          NJN    GSI10       IF MORE REGISTERS TO CHECK

*         CHECK CHANNEL 15/17 ERROR REGISTER.

          LDC    0#00B7
          RJM    CAB         CHECK IF ANY ERROR BITS SET

*         CHECK CLUSTER 0 BUS ARBITER ERROR REGISTER (0#009A).
*         BITS 9, 11, 12, 25, 27, 28 ALWAYS HAVE MEANING.
*         OTHER BITS HAVE MEANING ONLY IF BIT 39 IS SET IN ONE
*         OR MORE OF REGISTERS 0#0090 - 0#0094.

          LDC    0#009A
          STDL   RN
          RJM    GMB         READ REGISTER FROM SCRATCH MRB
          CRDL   CM
          LDM    BUS0        CHECK IF BIT 39 SET IN REGISTERS 90 - 94
          NJN    GSI12       IF ENTIRE REGISTER HAS MEANING
          LDDL   CM          PRESERVE BITS 9, 11, 12
          LPC    0#0058
          STDL   CM
          LDDL   CM+1        PRESERVE BITS 25, 27, 28
          LPC    0#0058
          STDL   CM+1
          LDN    0
          STDL   CM+2
          STDL   CM+3
 GSI12    LDN    0           SET REGISTER ALREADY READ
          RJM    CAB         CHECK IF ANY ERROR BITS SET

*         CHECK CLUSTER 2 BUS ARBITER ERROR REGISTER (0#00AA).
*         BITS 9, 11, 12, 25, 27, 28 ALWAYS HAVE MEANING.
*         OTHER BITS HAVE MEANING ONLY IF BIT 39 IS SET IN ONE
*         OR MORE OF REGISTERS 0#00A0 - 0#00A4.

          LDC    0#00AA
          STDL   RN
          RJM    GMB         READ REGISTER FROM SCRATCH MRB
          CRDL   CM
          LDM    BUS2        CHECK IF BIT 39 SET IN REGISTERS A0 - A4
          NJN    GSI13       IF ENTIRE REGISTER HAS MEANING
          LDDL   CM          PRESERVE BITS 9, 11, 12
          LPC    0#0058
          STDL   CM
          LDDL   CM+1        PRESERVE BITS 25, 27, 28
          LPC    0#0058
          STDL   CM+1
          LDN    0
          STDL   CM+2
          STDL   CM+3
 GSI13    LDN    0           SET REGISTER ALREADY READ
          RJM    CAB         CHECK IF ANY ERROR BITS SET

*         CHECK CLUSTER 0 ADU ERROR REGISTER (0#009B).
*         ONLY BITS 15, 31, 47 HAVE MEANING.

          LDC    0#009B
          STDL   RN
          RJM    GMB         READ REGISTER FROM SCRATCH MRB
          ZJN    GSI14       IF REGISTER NOT FOUND
          CRDL   CM
          LDDL   CM          PRESERVE BIT 15
          LPN    0#0001
          STDL   CM
          LDDL   CM+1        PRESERVE BIT 31
          LPN    0#0001
          STDL   CM+1
          LDDL   CM+2        PRESERVE BIT 47
          LPN    0#0001
          STDL   CM+2
          LDN    0
          STDL   CM+3
*         LDN    0           SET REGISTER ALREADY READ
          RJM    CAB         CHECK IF ANY ERROR BITS SET

*         CHECK CLUSTER 2 ADU ERROR REGISTER (0#00AB).
*         ONLY BITS 15, 31, 47 HAVE MEANING.

 GSI14    LDC    0#00AB
          STDL   RN
          RJM    GMB         READ REGISTER FROM SCRATCH MRB
          ZJN    GSI15       IF REGISTER NOT FOUND
          CRDL   CM
          LDDL   CM          PRESERVE BIT 15
          LPN    0#0001
          STDL   CM
          LDDL   CM+1        PRESERVE BIT 31
          LPN    0#0001
          STDL   CM+1
          LDDL   CM+2        PRESERVE BIT 47
          LPN    0#0001
          STDL   CM+2
          LDN    0
          STDL   CM+3
*         LDN    0           SET REGISTER ALREADY READ
          RJM    CAB         CHECK IF ANY ERROR BITS SET

*         COMPLETE GENERATION OF FAULT SYMPTOM CODE.

 GSI15    LDC    2RDI        SET FAULT SYMPTOM CODE PREFIX
          RJM    GFS         GENERATE FAULT SYMPTOM CODE
          LJM    GSIX        RETURN
 GSM      SPACE  4,10
**        GSM - GENERATE FAULT SYMPTOM CODE FOR MEMORY ERROR.
*
*         ENTRY  SCRATCH MRB CONTAINS LOGGED REGISTERS.


          ROUTINE  GSM

          LDDL   BC+BCDA
          SHN    -BC.ANP
          SBN    EPEN
          MJP    GSM0        IF NOT ENVIRONMENT ERROR
          LDC    2RDM
          RJM    WFC         WRITE FAULT CODE
          LJM    GSMX        RETURN

 GSM0     LDN    0           INITIALIZE VALUES
          STM    BITN        INITIALIZE BIT NUMBER OF FIRST ERROR
          STM    REGC        INITIALIZE NUMBER OF REGISTERS WITH ERROR(S)
          STM    REGN        INITIALIZE REGISTER NUMBER WITH FIRST ERROR

*         CHECK UNCORRECTED CM INTERFACE BOARD ERROR REGISTER.

          LDC    0#1090
          STDL   RN
          RJM    GMB         READ REGISTER FROM SCRATCH MRB
          CRDL   CM
          LDDL   CM          CHECK BIT 0
          SHN    21-17
          PJN    GSM1        IF NO ERROR LOGGED
          LDN    0           PROCESS REGISTER CONTENTS
          RJM    CAB

*         CHECK UNCORRECTED CM BOARD ERROR REGISTERS.
*         IF BIT 0 = 1, BITS 1 - 15 HAVE MEANING.
*         IF BIT 16 = 1, BITS 17 - 31 HAVE MEANING.

 GSM1     LDN    0           INITIALIZE REGISTER LOOP
          STD    W0
 GSM2     LDML   GSMA,W0     CHECK NEXT REGISTER
          ZJN    GSM6        IF END OF LIST
          STDL   RN
          RJM    GMB         READ REGISTER FROM SCRATCH MRB
          ZJN    GSM5        IF REGISTER NOT FOUND
          CRDL   CM
          LDDL   CM          CHECK BIT 0
          LPC    0#8000
          NJN    GSM3        IF ERRORS LOGGED IN BITS 1 - 15
*         LDN    0           CLEAR BITS 0 - 15
          STDL   CM
 GSM3     LDDL   CM+1        CHECK BIT 16
          LPC    0#8000
          NJN    GSM4        IF ERRORS LOGGED IN BITS 17 - 31
*         LDN    0           CLEAR BITS 16 - 31
          STDL   CM+1
 GSM4     LDN    0           CLEAR UNUSED BITS
          STD    CM+2
          STD    CM+3
*         LDN    0           SET REGISTER ALREADY READ
          RJM    CAB         CHECK IF ANY ERROR BITS SET
 GSM5     AOD    W0          ADVANCE REGISTER LIST INDEX
          UJN    GSM2        LOOP FOR ALL REGISTERS IN LIST

*         CHECK UNCORRECTED CM BANK ERROR REGISTERS (10AX, 10BX, 10CX).
*         IF BIT 16 OF REGISTER 10AX = 1, REGISTERS 10AX, 10BX, 10CX
*         HAVE MEANING.

 GSM6     LDC    0#10A0      INITIALIZE REGISTER LOOP
          STDL   W0
 GSM7     LDDL   W0          CHECK NEXT REGISTER
          STDL   RN
          RJM    GMB         READ REGISTER FROM SCRATCH MRB
          ZJN    GSM9        IF REGISTER NOT FOUND
          CRDL   CM
          LDDL   CM+1        CHECK BIT 16
          LPC    0#8000
          ZJN    GSM9        IF NO ERRORS LOGGED
          LDN    0           SET REGISTER ALREADY READ
          RJM    CAB         CHECK IF ANY ERROR BITS SET
          LDDL   W0          CHECK REGISTER 10BX
          ADN    0#10B0-0#10A0
          RJM    CAB
          LDDL   W0          CHECK REGISTER 10CX
          ADN    0#10C0-0#10A0
          RJM    CAB
 GSM9     AODL   W0          ADVANCE REGISTER NUMBER
          LMC    0#10AF+1
          NJN    GSM7        IF MORE REGISTERS TO CHECK

*         CHECK CORRECTED CM BANK ERROR REGISTERS (10DX, 10EX).
*         IF BIT 16 OF REGISTER 10DX = 1, REGISTERS 10DX, 10EX
*         HAVE MEANING.

          LDC    0#10D0      INITIALIZE REGISTER LOOP
          STDL   W0
 GSM10    LDDL   W0          CHECK NEXT REGISTER
          STDL   RN
          RJM    GMB         READ REGISTER FROM SCRATCH MRB
          ZJN    GSM12       IF REGISTER NOT FOUND
          CRDL   CM
          LDDL   CM+1        CHECK BIT 16
          LPC    0#8000
          ZJN    GSM12       IF NO ERRORS LOGGED
          LDN    0           SET REGISTER ALREADY READ
          RJM    CAB         CHECK IF ANY ERROR BITS SET
          LDDL   W0          CHECK REGISTER 10EX
          ADN    0#10E0-0#10D0
          RJM    CAB
 GSM12    AODL   W0          ADVANCE REGISTER NUMBER
          LMC    0#10DF+1
          NJN    GSM10       IF MORE REGISTERS TO CHECK

*         COMPLETE GENERATION OF FAULT SYMPTOM CODE.

          LDC    2RDM        SET FAULT SYMPTOM CODE PREFIX
          RJM    GFS         GENERATE FAULT SYMPTOM CODE
          LJM    GSMX        RETURN

 GSMA     DATA   0#1091,0#1095,0#1092,0#1096  UNCORRECTED CM BOARD ERRORS
          DATA   0#1093,0#1097,0#1094,0#1098
          DATA   0           END OF LIST
 GSP      SPACE  4,10
**        GSP - GENERATE FAULT SYMPTOM CODE FOR PAGE MAP ERROR.
*
*         ENTRY  SCRATCH MRB CONTAINS LOGGED REGISTERS.


          ROUTINE  GSP

          LDN    0           INITIALIZE VALUES
          STM    BITN        INITIALIZE BIT NUMBER OF FIRST ERROR
          STM    REGC        INITIALIZE NUMBER OF REGISTERS WITH ERROR(S)
          STM    REGN        INITIALIZE REGISTER NUMBER WITH FIRST ERROR

*         CHECK FIRST FAILURE CAPTURE AND ACCUMULATED ERROR REGISTERS.

          LDC    0#309C
          RJM    CAB         CHECK IF ANY ERROR BITS SET
          LDC    0#309D
          RJM    CAB         CHECK IF ANY ERROR BITS SET

*         CHECK DETAILED ERROR REGISTERS (0#3090 - 0#309B).

          LDC    0#3090      INITIALIZE REGISTER LOOP
          STDL   W0
 GSP1     LDDL   W0          CHECK NEXT REGISTER
          RJM    CAB         CHECK IF ANY ERROR BITS SET
          AODL   W0          ADVANCE REGISTER NUMBER
          LMC    0#309B+1
          NJN    GSP1        IF MORE REGISTERS TO CHECK

*         COMPLETE GENERATION OF FAULT SYMPTOM CODE.

          LDC    2RDP        SET FAULT SYMPTOM CODE PREFIX
          RJM    GFS         GENERATE FAULT SYMPTOM CODE
          LJM    GSPX        RETURN
 CAB      SPACE  4,10
**        CAB - CHECK FOR ANY BIT SET IN REGISTER.
*
*         ENTRY  (A) = REGISTER NUMBER TO CHECK.
*                    = 0, IF REGISTER DATA ALREADY PRESENT IN (CM - CM+3).
*
*         EXIT   (RN) = REGISTER NUMBER.
*                (REGC) ADVANCED IF ANY BITS SET IN REGISTER.
*
*         USES   CM - CM+3, T4, T4, T6.
*
*         CALLS  GMB, RRB.


 CAB      SUBR               ENTRY/EXIT
          ZJN    CAB1        IF DATA ALREADY PRESENT
          STDL   RN          SAVE REGISTER NUMBER
          RJM    GMB         READ REGISTER FROM SCRATCH MRB
          ZJN    CABX        IF REGISTER NOT PRESET IN SCRATCH MRB
          CRDL   CM
 CAB1     LDDL   CM+0        CHECK IF ANY BITS SET
          ADDL   CM+1
          ADDL   CM+2
          ADDL   CM+3
          ZJN    CABX        IF NO ERROR BITS SET IN REGISTER
          AOM    REGC        ADVANCE COUNT OF REGISTERS WITH ERROR(S)
          LDN    0           INITIALIZE PP WORD OFFSET
          STD    T4
          STD    T5          INITIALIZE BIT NUMBER
          LDC    0#8000      INITIALIZE MASK
          STDL   T6
 CAB2     LDML   CM,T4       GET APPROPRIATE PP WORD
          LPDL   T6          CHECK NEXT BIT
          ZJN    CAB3        IF BIT NOT SET
          RJM    RRB         RECORD REGISTER AND BIT NUMBER
 CAB3     AOD    T5          ADVANCE BIT NUMBER
          LDDL   T6          SHIFT MASK
          SHN    -1
          STDL   T6
          NJN    CAB2        IF MORE BITS TO CHECK IN CURRENT PP WORD
          LDC    0#8000      REINITIALIZE MASK
          STDL   T6
          AOD    T4          ADVANCE TO NEXT PP WORD
          LMN    4
          NJN    CAB2        IF MORE PP WORDS TO CHECK
          LJM    CABX        RETURN
 WFC      SPACE  4,10
**        WFC - WRITE FAULT SYMPTOM CODE.
*
*         ENTRY  (A) = TWO CHARACTER ELEMENT IDENTIFIER.
*                (BC - BC+3) = BUFFER CONTROL WORD.
*                (RTP1) = 0 LOG TO SUPPORTIVE STATUS
*                       = 1 LOG TO NON REGISTER STATUS
*         USES   T1, CM - CM+3.
*
*         CALLS  CDA, CSD, IDA.


 WFC      SUBR               ENTRY/EXIT
          STDL   T1          SAVE ELEMENT IDENTIFIER
          LDN    3
          STM    WFCC        NUMBER OF HEADER WORDS FOR SUPPORTIVE STATUS
          LDM    RTP1        FLAG TO LOG TO SUPPORTIVE STATUS OR NON REGISTER STATUS
          ZJN    WFC1        IF TO LOG TO SUPPORTIVE STATUS
          AOM    WFCC        NON REGISTER STATUS HAS 1 MORE HEADER WORD THAN SUPPORTIVE
          LDN    NRSP        ADDRESS OF SCRATCH NON REGISTER STATUS BUFFER
          UJN    WFC2

*         READ FIRST WORD OF FAULT SYMPTOM CODE TO PRESERVE FIRST TWO BYTES.

 WFC1     LDN    SSBP        GET ADDRESS OF SCRATCH BUFFER
 WFC2     RJM    IDA
          CRDL   CM
          LDM    WFCC        SKIP HEADER WORDS
          RADL   CM
          LRD    CM+1
          ADC    RR
          CRML   WFCA,ON
          LDDL   T1          SET ELEMENT IDENTIFIER
          STML   WFCB

*         SET MODEL NUMBER.

          LDD    MD
          RJM    CDA         CONVERT TWO DIGITS TO ASCII
          STML   WFCB+1

*         SET SYMPTOM CODE.

          LDDL   BC+BCDA     DFT ANALYSIS
          SHN    -10
          LPN    0#F
          STD    T1
          LMN    4           4XX INTERNAL ERROR
          ZJN    WFC2.5      IF INTERNAL ERROR
          LDD    T1
          LMN    5           5XX INTERNAL ERROR
          ZJN    WFC2.5      IF INTERNAL ERROR
          LDD    T1
          LMN    6           6XX CODE
          ZJN    WFC2.5      IF INTERNAL ERROR
          UJN    WFC3

 WFC2.5   LDML   WFCB+2
          LPC    0#FF00
          STML   WFCB+2
          LDDL   BC+BCDA
          SHN    -10
          LPN    0#F
          RJM    CSD         CONVERT SINGLE DIGIT
          LMML   WFCB+2
          STML   WFCB+2
          LDDL   BC+BCDA
          LPC    0#FF
          RJM    CDA         CONVERT DIGITS TO ASCII
          STML   WFCB+3
          UJP    WFC4

 WFC3     LDDL   BC+BCDA     DFT ANALYSIS
          SHN    -4          ISOLATE FIRST TWO CHARACTERS
          LPC    377
          RJM    CDA         CONVERT TWO DIGITS TO ASCII
          STML   WFCB+2
          LDD    BC+BCDA     ISOLATE LAST CHARACTER
          LPN    17
          RJM    CSD         CONVERT SINGLE DIGIT TO ASCII
          SHN    10
          LMC    1R
          STML   WFCB+3

*         WRITE FAULT SYMPTOM CODE TO SCRATCH SUPPORTIVE STATUS BUFFER.

 WFC4     LDN    2           SET NUMBER OF CM WORDS TO WRITE
          STD    T1
          LDDL   CM          LOAD ADDRESS OF SCRATCH BUFFER
          ADC    RR
          CWML   WFCA,T1     WRITE TO SCRATCH BUFFER
          LJM    WFCX        RETURN

 WFCC     BSS    1
 WFCA     BSS    2           RESERVED AREA OF FAULT SYMPTOM CODE
 WFCB     DATA   12HDEMMZCC
 CDD      SPACE  4,10
***       CDD - CONVERT VALUE TO TWO DECIMAL ASCII DIGITS.
*
*         ADAPTED FROM NOS COMMON DECK *COMPCDD*.
*
*         ENTRY  (A) = VALUE TO BE CONVERTED.
*
*         EXIT   (A) = DECIMAL ASCII EQUIVALENT, IF NO ERROR.
*                    = 2R** IF VALUE OUTSIDE RANGE OF 00 - 99.


 CDD3     LDC    2R**        SET (A) = RANGE ERROR

 CDD      SUBR               ENTRY/EXIT
          MJN    CDD3        IF VALUE NEGATIVE
          STD    T0
          SBK    99D+1       CHECK RANGE
          PJN    CDD3        IF VALUE GREATER THAN 99
          LDC    2R00+10D    INITIALIZE ASSEMBLY
          STML   CDDA
 CDD1     LCN    10D         DECREMENT ANOTHER 10
          RAD    T0
          MJN    CDD2        IF REMAINDER .LT. 10
          LDC    1S8         ADVANCE TENS DIGIT
          RAML   CDDA
          UJN    CDD1        LOOP

 CDD2     ADC    2R00+10D    ASSEMBLE TENS AND ONES DIGITS
 CDDA     EQU    *-1
          UJN    CDDX        RETURN
 GFS      SPACE  4,10
**        GFS - GENERATE FAULT SYMPTOM CODE.
*
*         ENTRY  (A) = TWO CHARACTER FAULT SYMPTOM CODE PREFIX.
*                (BITN) = FIRST ERROR BIT SET.
*                (REGC) = NUMBER OF REGISTERS WITH ERROR BIT(S) SET.
*                (REGN) = FIRST REGISTER WITH ERROR BIT(S) SET.
*
*         EXIT   FAULT SYMPTOM CODE WRITTEN TO SUPPORTIVE STATUS BUFFER.
*
*         USES   CM - CM+3, T0, T2, W0 - W0+7.
*
*         CALLS  CDA, CDD, IDA.
*
*         NOTE   SINCE S0/S0E USE THE SAME MODEL NUMBER FOR ALL ELEMENTS,
*                THE IOU MODEL NUMBER WILL BE USED REGARDLESS OF ELEMENT.


 GFS      SUBR               ENTRY/EXIT
          STML   GFSA        SAVE FAULT SYMPTOM CODE PREFIX
          LDN    2           SET NUMBER OF CM WORDS TO READ/WRITE
          STD    T2
          LDN    SSBP        GET ADDRESS OF SCRATCH ENTRY
          RJM    IDA
          CRDL   CM
          LDN    3           SKIP HEADER WORDS
          RADL   CM
          LRD    CM+1
          ADC    RR
          CRML   W0,T2       READ EXISTING WORDS

*         ASSEMBLE FAULT SYMPTOM CODE IN (W0 - W0+7).

          LDML   GFSA        SET FAULT SYMPTOM CODE PREFIX
          STDL   W0+2
          LDM    IOUM        SET MODEL NUMBER
          RJM    CDA         CONVERT TWO HEX DIGITS TO ASCII
          STDL   W0+3
          LDML   REGN        SET REGISTER TYPE AND UPPER HEX DIGIT OF ERROR REG.
          SHN    -4
          RJM    CDA         CONVERT TWO HEX DIGITS TO ASCII
          STDL   W0+4
          LDML   REGN        SET LOWER HEX DIGIT OF ERROR REGISTER
          RJM    CDA         CONVERT TWO HEX DIGITS TO ASCII
          LPC    0#FF
          SHN    10          POSITION LOWER HEX DIGIT OF ERROR REGISTER
          STDL   W0+5
          LDM    BITN        SET BIT NUMBER
          RJM    CDD         CONVERT TWO DECIMAL DIGITS TO ASCII
          STDL   T0          SAVE CONVERTED VALUE
          SHN    -10
          RADL   W0+5        MERGE WITH LOWER DIGIT OF ERROR REGISTER
          LDDL   T0          STORE LOWER DIGIT OF BIT NUMBER
          LPC    0#FF
          SHN    10
          STDL   W0+6
          LDM    REGC        SET NUMBER OF REGISTERS WITH ERRORS
          RJM    CDD         CONVERT TWO DECIMAL DIGITS TO ASCII
          STDL   T0          SAVE CONVERTED VALUE
          SHN    -10
          RADL   W0+6        MERGE WITH LOWER DIGIT OF BIT NUMBER
          LDDL   T0          STORE LOWER DIGIT OF NUMBER OF REGISTERS
          LPC    0#FF
          SHN    10
          ADC    1R          BLANK FILL LAST FIELD
          STDL   W0+7

*         WRITE COMPLETED FAULT SYMPTOM CODE TO SUPPORTIVE STATUS BUFFER.

          LDD    CM          REWRITE SUPPORTIVE STATUS BUFFER ENTRY
          ADC    RR
          CWML   W0,T2
          LJM    GFSX        RETURN

 GFSA     BSS    1           SAVE AREA FOR FAULT SYMPTOM CODE PREFIX
 GMB      SPACE  4,10
**        GMB - GET MAINTENANCE REGISTER FROM SCRATCH BUFFER.
*
*         THIS ROUTINE IS A MODIFIED VERSION OF *FMB* WHICH EXAMINES ALL
*         16 BITS OF THE REGISTER HEADER AND RETURNS (A) = 0 IF THE
*         REGISTER IS NOT FOUND INSTEAD OF REPORTING A 607 ERROR.
*
*         ENTRY  (A) = MAINTENANCE REGISTER TO FIND.
*
*         EXIT   (A) AND (R) SET FOR ACCESS.
*                (A) = 0 IF REGISTER NOT FOUND IN SCRATCH MRB.
*
*         CALLS  IMB.


 GMB      SUBR               ENTRY/EXIT
          STML   GMBB        SAVE REGISTER TO BE FOUND
          LDN    0           INITIALIZE FOR FIRST REGISTER GROUP
          STM    GMBC

*         READ NEXT HEADER WORD.

 GMB1     RJM    IMB         READ HEADER WORD
          CRML   GMBD,ON
          LDC    GMBD        INITIALIZE SEARCH LOOP
          STM    GMBA

*         CHECK IF REGISTER IS IN THIS REGISTER GROUP.

 GMB2     LDML   **          CHECK NEXT REGISTER DESCRIPTOR
 GMBA     EQU    *-1         (HEADER BYTE TO CHECK)
          LMML   GMBB
          ZJN    GMB3        IF REGISTER FOUND
          AOM    GMBA
          LMC    GMBD+4
          NJN    GMB2        IF MORE BYTES IN CURRENT HEADER WORD
          LDN    5           ADVANCE TO NEXT HEADER WORD
          RAM    GMBC
          SBM    LBUF        SUBTRACT LENGTH OF BUFFER FROM PRESENT LOCATION
          ZJN    GMBX        IF AT END OF BUFFER
          LDM    GMBC
          UJN    GMB1        LOOP

*         SET RETURN PARAMETERS FOR REGISTER ADDRESS IN GROUP.

 GMB3     LDM    GMBC        SET OFFSET FOR REGISTER GROUP
          ADN    1
          ADM    GMBA        INCLUDE WORD OFFSET IN FOUR REGISTER GROUP
          ADC    -GMBD
          RJM    IMB         SET (A) AND (R) FOR ACCESS
          LJM    GMBX        RETURN

 GMBB     BSS    1           REGISTER TO LOCATE
 GMBC     BSS    1           HEADER ADDRESS IN BUFFER
 GMBD     BSS    4           HEADER WORD BUFFER
 RRB      SPACE  4,10
**        RRB - RECORD REGISTER NUMBER AND BIT NUMBER.
*
*         ENTRY  (T5) = BIT NUMBER.
*                (RN) = REGISTER NUMBER.
*
*         EXIT   (REGN) = REGISTER NUMBER, IF NOT PREVIOUSLY SET.
*                (BITN) = BIT NUMBER, IF NOT PREVIOUSLY SET.


 RRB      SUBR               ENTRY/EXIT
          LDM    REGN        CHECK FOR PREVIOUS ERROR BIT
          NJN    RRBX        IF PREVIOUS ERROR RECORDED
          LDDL   RN          SAVE REGISTER NUMBER
          STML   REGN
          LDD    T5          SAVE BIT NUMBER
          STM    BITN
          UJN    RRBX        RETURN
 COMMON   SPACE  4,10
*         COMMON DECKS.


*COPY     CTP$CONVERT_DIGITS_TO_ASCII

          QUAL   *

          OVERFLOW  10000    CHECK FOR OVERFLOW
          OVERLAY  (LOG ERROR TO BUFFER CONTROL WORDS)
*COPYC CTP$DFT_LOG_ERROR
*COPY CTP$DFT_INCREMENT_ERROR_COUNT
*COPY  CTP$DFT_FIND_WARNING_IN_NRSB
*COPY CTP$DFT_FIND_CONTROL_WORD
*COPY CTP$DFT_LOG_ERROR_CHECK_MATCH
*COPYC CTP$DFT_LOG_PACKET_TO_CONSOLE
*COPY  CTP$DFT_CHECK_PKTS_FOR_S0
*COPY CTC$DFT_ELEMENT_CONVERSIONS
*COPY CTP$DFT_ZERO_SUPPORTIVE_STATUS
 ABL      SPACE  4,10
**        ABL - ADJUST BUFFER LENGTH.
*
*         THIS IS A DUMMY ROUTINE ON S0/S0E.


 ABL      SUBR               ENTRY/EXIT
          UJN    ABLX        RETURN
 URC      SPACE  4,10
**        URC - UPDATE RETRY COUNTERS.
*
*         THIS IS A DUMMY ROUTINE ON S0/S0E.


 URC      SUBR               ENTRY/EXIT
          UJN    URCX        RETURN
          QUAL   *

          OVERFLOW  10000    CHECK FOR OVERFLOW
          OVERLAY  (READ MAINTENANCE REGISTERS)
          QUAL   *           SO THAT OTHER OVERLAYS MAY ACCESS
 RLCIE0   SPACE  4,10
**        RLCIE0 - REGISTER LIST FOR CORRECTED IOU ERROR - CLUSTER 0.
*
*         NOTE - AT THIS TIME THE CORRECTED/UNCORRECTED LISTS MATCH.


 RLCIE0   REGLST (10,00,12,20,21,22,23,24,2A,2B,40,41,50,51,52,53,54
,,70,71,72,73,74,90,91,92,93,94,9A,9B,B0,B1,B2,B7)
 RLCIE2   SPACE  4,10
**        RLCIE2 - REGISTER LIST FOR CORRECTED IOU ERROR - CLUSTERS 0/2.
*
*         NOTE - AT THIS TIME THE CORRECTED/UNCORRECTED LISTS MATCH.


 RLCIE2   REGLST (10,00,12,20,21,22,23,24,2A,2B,40,41,42,50,51,52,53,54
,,70,71,72,73,74,30,31,32,33,34,3A,3B,48,49,4A,60,61,62,63,64,80,81,82
,,83,84,90,91,92,93,94,9A,9B,B0,B1,B2,B7,A0,A1,A2,A3,A4,AA,AB,B8,B9,BA)
 RLCME    SPACE  4,10
**        RLCME - REGISTER LIST FOR CORRECTED MEMORY ERROR.
*
*         ADDITIONAL REGISTERS WILL BE LOGGED FOR THE SPECIFIC ERROR.


 RLCME    REGLST (10,00,12,58,20)
 RLCPE    SPACE  4,10
**        RLCPE - REGISTER LIST FOR CORRECTED S0 PROCESSOR ERROR.


 RLCPE    REGLST (10,00,12,20,21,22,23,24,25,26,27,28,29,2A,2B,2C,2D,2E
,,2F,30,31,32,33,34,90,91,92,93,94,95,96,97,98,99,9A,9B,9C,9D,9E,9F
,,A0,A1,A2,A3,A4,A5,A6,A7,A8,A9,AA,AB,AC,AD,AE,C0,880,881,890,891)
 RLCPE    SPACE  4,10
**        RLCPE - REGISTER LIST FOR CORRECTED S0E PROCESSOR ERROR.


          QUAL   S0E
 RLCPE    REGLST (10,00,12,20,21,22,23,24,25,26,27,28,29,2A,2B,2C,2D,2E
,,2F,90,91,92,93,94,95,96,97,98,99,9A,9B,9C,9D,9E,9F,A0,A1,A2,A3,A4,A5
,,A6,A7,C0,880,881,890,891)
          QUAL   *
 RLUIE0   SPACE  4,10
**        RLUIE0 - REGISTER LIST FOR UNCORRECTED IOU ERROR - CLUSTER 0.
*
*         NOTE - AT THIS TIME THE CORRECTED/UNCORRECTED LISTS MATCH.


 RLUIE0   REGLST (10,00,12,20,21,22,23,24,2A,2B,40,41,50,51,52,53,54
,,70,71,72,73,74,90,91,92,93,94,9A,9B,B0,B1,B2,B7)
 RLUIE2   SPACE  4,10
**        RLUIE2 - REGISTER LIST FOR UNCORRECTED IOU ERROR - CLUSTERS 0/2.
*
*         NOTE - AT THIS TIME THE CORRECTED/UNCORRECTED LISTS MATCH.


 RLUIE2   REGLST (10,00,12,20,21,22,23,24,2A,2B,40,41,42,50,51,52,53,54
,,70,71,72,73,74,30,31,32,33,34,3A,3B,48,49,4A,60,61,62,63,64,80,81,82
,,83,84,90,91,92,93,94,9A,9B,B0,B1,B2,B7,A0,A1,A2,A3,A4,AA,AB,B8,B9,BA)
 RLUME    SPACE  4,10
**        RLUME - REGISTER LIST FOR UNCORRECTED MEMORY ERROR.
*
*         ADDITIONAL REGISTERS WILL BE LOGGED FOR THE SPECIFIC ERROR.


 RLUME    REGLST (10,00,12,58,20,90)
 RLUPE    SPACE  4,10
**        RLUPE - REGISTER LIST FOR UNCORRECTED S0 PROCESSOR ERROR.


 RLUPE    REGLST (10,00,12,20,21,22,23,24,25,26,27,28,29,2A,2B,2C,2D,2E
,,2F,30,31,32,33,34,90,91,92,93,94,95,96,97,98,99,9A,9B,9C,9D,9E,9F
,,A0,A1,A2,A3,A4,A5,A6,A7,A8,A9,AA,AB,AC,AD,AE,880,881,890,891)
 RLUPE    SPACE  4,10
**        RLUPE - S0E REGISTER LIST FOR UNCORRECTED PROCESSOR ERROR.


          QUAL   S0E
 RLUPE    REGLST (10,00,12,20,21,22,23,24,25,26,27,28,29,2A,2B,2C,2D,2E
,,2F,90,91,92,93,94,95,96,97,98,99,9A,9B,9C,9D,9E,9F,A0,A2,A3,A3,A4,A5
,,A6,A7,880,881,890,891)
          QUAL   *
 PM0      SPACE  4,10
**        S0/S0E PAGE MAP *DEC* REGISTERS.


 PM0      REGLST (90,91,92,93,94,95,96,97,98,99,9A,9B,9C,9D)
 PPM0     SPACE  4,10
**        S0/S0E PROCESSOR PAGE MAP REGISTERS.


 PPM0     REGLST (00,881,891)
 PD0      SPACE  4,10
**        S0/S0E PAGE MAP DEC REGISTERS.


 PD0      REGLST (20,21,22,23,24,25,26,27)
 MPMD0    SPACE  4,10
**        MEMORY PAGE MAP REGISTERS.


 MPMD0    REGLST (10,0,12)
 S0MCV    SPACE  4,10
**        S0/S0E MEMORY CORRECTED ERROR REGISTER LIST - VARIABLE REGISTERS.
*
*         THE EXACT REGISTERS LOGGED DEPEND ON THE BOARD/BANK INVOLVED.
*         THE FORMAT IS MC00 FOR BOARD 0 BANK 0, MC01 FOR BOARD 0 BANK 1, ETC.


 MC00     REGLST (21,25,30,60,D0,E0)
          SPACE  4,10
 MC01     REGLST (21,25,31,61,D1,E1)
          SPACE  4,10
 MC02     REGLST (21,25,32,62,D2,E2)
          SPACE  4,10
 MC03     REGLST (21,25,33,63,D3,E3)
          SPACE  4,10
 MC10     REGLST (22,26,34,64,D4,E4)
          SPACE  4,10
 MC11     REGLST (22,26,35,65,D5,E5)
          SPACE  4,10
 MC12     REGLST (22,26,36,66,D6,E6)
          SPACE  4,10
 MC13     REGLST (22,26,37,67,D7,E7)
          SPACE  4,10
 MC20     REGLST (23,27,38,68,D8,E8)
          SPACE  4,10
 MC21     REGLST (23,27,39,69,D9,E9)
          SPACE  4,10
 MC22     REGLST (23,27,3A,6A,DA,EA)
          SPACE  4,10
 MC23     REGLST (23,27,3B,6B,DB,EB)
          SPACE  4,10
 MC30     REGLST (24,28,3C,6C,DC,EC)
          SPACE  4,10
 MC31     REGLST (24,28,3D,6D,DD,ED)
          SPACE  4,10
 MC32     REGLST (24,28,3E,6E,DE,EE)
          SPACE  4,10
 MC33     REGLST (24,28,3F,6F,DF,EF)
          SPACE  4,10
**        S0/S0E MEMORY UNCORRECTED BOARD LEVEL ERROR REGISTER LISTS.


 MUB0     REGLST (21,25,30,31,32,33,60,61,62,63,91,95,A0,A1,A2,A3,B0
,,B1,B2,B3,C0,C1,C2,C3)
          SPACE  4,10
 MUB1     REGLST (22,26,34,35,36,37,64,65,66,67,92,96,A4,A5,A6,A7,B4
,,B5,B6,B7,C4,C5,C6,C7)
          SPACE  4,10
 MUB2     REGLST (23,27,38,39,3A,3B,68,69,6A,6B,93,97,A8,A9,AA,AB,B8
,,B9,BA,BB,C8,C9,CA,CB)
          SPACE  4,10
 MUB3     REGLST (24,28,3C,3D,3E,3F,6C,6D,6E,6F,94,98,AC,AD,AE,AF,BC
,,BD,BE,BF,CC,CD,CE,CF)
 S0MUV    SPACE  4,10
**        S0/S0E MEMORY UNCORRECTED ERROR REGISTER LIST - VARIABLE REGISTERS.
*
*         THE EXACT REGISTERS LOGGED DEPEND ON THE BOARD/BANK INVOLVED.
*         THE FORMAT IS MU00 FOR BOARD 0 BANK 0, MU01 FOR BOARD 0 BANK 1, ETC.


 MU00     REGLST (21,25,30,60,91,95,A0,B0,C0)
          SPACE  4,10
 MU01     REGLST (21,25,31,61,91,95,A1,B1,C1)
          SPACE  4,10
 MU02     REGLST (21,25,32,62,91,95,A2,B2,C2)
          SPACE  4,10
 MU03     REGLST (21,25,33,63,91,95,A3,B3,C3)
          SPACE  4,10
 MU10     REGLST (22,26,34,64,92,96,A4,B4,C4)
          SPACE  4,10
 MU11     REGLST (22,26,35,65,92,96,A5,B5,C5)
          SPACE  4,10
 MU12     REGLST (22,26,36,66,92,96,A6,B6,C6)
          SPACE  4,10
 MU13     REGLST (22,26,37,67,92,96,A7,B7,C7)
          SPACE  4,10
 MU20     REGLST (23,27,38,68,93,97,A8,B8,C8)
          SPACE  4,10
 MU21     REGLST (23,27,39,69,93,97,A9,B9,C9)
          SPACE  4,10
 MU22     REGLST (23,27,3A,6A,93,97,AA,BA,CA)
          SPACE  4,10
 MU23     REGLST (23,27,3B,6B,93,97,AB,BB,CB)
          SPACE  4,10
 MU30     REGLST (24,28,3C,6C,94,98,AC,BC,CC)
          SPACE  4,10
 MU31     REGLST (24,28,3D,6D,94,98,AD,BD,CD)
          SPACE  4,10
 MU32     REGLST (24,28,3E,6E,94,98,AE,BE,CE)
          SPACE  4,10
 MU33     REGLST (24,28,3F,6F,94,98,AF,BF,CF)

*COPYC CTP$DFT_READ_MAINTENANCE_REGS
 ZSS      SPACE  4,10
**        ZSS - ZERO SUPPORTIVE STATUS.
*
*         NOTE   THIS ROUTINE IS INOPERATIVE ON A CYBER 180-930 SERIES.


 ZSS      SUBR               ENTRY/EXIT
          UJN    ZSSX        RETURN

          OVERFLOW  10000    CHECK FOR OVERFLOW
          OVERLAY  (PROCESSOR PRIMITIVES)
*COPY CTP$DFT_PROCESSOR_PRIMITIVES
*         THE FOLLOWING ROUTINES ARE STUBS BECAUSE THEY ARE
*         NOT NEEDED ON S0/S0E.

          ROUTINE  STRBTS

          LJM    STRBTSX     RETURN


 CLRBTS   SUBR               ENTRY/EXIT
          UJN    CLRBTSX     RETURN
 DIP      SPACE  4,10
**        DIP - DISABLE MEMORY PORT FOR PROCESSOR WITH FATAL ERROR.
*
*         ENTRY  (HBUF) = PROCESSOR INFORMATION.
*
*         NOTE   THIS ROUTINE IS IDENTICAL TO *DMP* EXCEPT THAT THE
*                PROCESSOR IS NOT MASTER CLEARED.


          ROUTINE  DIP

          LOCKMR SET         ACQUIRE INTERLOCK
          LDM    S0EFLG      CHECK CPU TYPE
          NJP    DIP1        IF S0E

*         DISABLE MEMORY PORT FOR S0 PROCESSOR.

          READMR RDATA,CMCC,ECMR  READ MEMORY ENVIRONMENT CONTROL
          LDM    RDATA       SET BITS 3, 4
          LPC    0#E7
          LMN    0#18
          STM    RDATA
          WRITMR RDATA,CMCC  REWRITE *EC* REGISTER
          LJM    DIP2        RELEASE INTERLOCK AND RETURN

*         DISABLE PAGE MAP PORT FOR S0E PROCESSOR.

 DIP1     LDM    HBUF+CPRPC  DETERMINE CPU NUMBER
          LPN    1
          STD    T1
          READMR RDATA,S0PMC,S0PPMC  READ PAGE MAP CONTROL REGISTER
          LDM    RDATA+1     SET BIT 8 OR 9 DEPENDING ON CPU NUMBER
          LPML   DIPA,T1
          LMM    DIPB,T1
          STM    RDATA+1
          WRITMR RDATA,S0PMC REWRITE PAGE MAP CONTROL REGISTER

*         COMMON EXIT.

 DIP2     LOCKMR CLEAR       RELEASE INTERLOCK
          LJM    DIPX        RETURN

 DIPA     CON    0#7F,0#BF   CLEAR CPU PORT DISABLE BIT MASK
 DIPB     CON    0#80,0#40   SET CPU PORT DISABLE BIT MASK
 DMP      SPACE  4,10
**        DMP - DISABLE MEMORY PORT.
*
*         ENTRY  (HBUF) = PROCESSOR INFORMATION.


          ROUTINE  DMP

          LOCKMR SET         ACQUIRE INTERLOCK
          LDM    S0EFLG      CHECK CPU TYPE
          NJP    DMP1        IF S0E

*         DISABLE MEMORY PORT FOR S0 PROCESSOR.

          LDDL   EC          SAVE REGISTER VALUE
          STDL   W0
          LDN    ECMR        *READMR RDATA,CMCC,ECMR*
          STDL   RN
          LDML   CMCC
          RJM    RMR         READ MAINTENANCE REGISTER
          LDM    RDATA       SET BITS 3, 4
          LPC    0#E7
          LMN    0#18
          STM    RDATA
          WRITMR RDATA       REWRITE *EC* REGISTER
          LDDL   W0          RESTORE *EC* DIRECT CELL
          STDL   EC
          LJM    DMP2        RELEASE INTERLOCK AND RETURN

*         DISABLE PAGE MAP PORT FOR S0E PROCESSOR.

 DMP1     LDM    HBUF+CPRPC  DETERMINE CPU NUMBER
          LPN    1
          STD    T1
          READMR RDATA,S0PMC,S0PPMC  READ PAGE MAP CONTROL REGISTER
          LDM    RDATA+1     SET BIT 8 OR 9 DEPENDING ON CPU NUMBER
          LPML   DMPA,T1
          LMM    DMPB,T1
          STM    RDATA+1
          WRITMR RDATA,S0PMC REWRITE PAGE MAP CONTROL REGISTER

*         COMMON EXIT.

 DMP2     FUNCMR HBUF+CPRPC,MRMC  MASTER CLEAR PROCESSOR
          LOCKMR CLEAR       RELEASE INTERLOCK
          LJM    DMPX        RETURN

 DMPA     CON    0#7F,0#BF   CLEAR CPU PORT DISABLE BIT MASK
 DMPB     CON    0#80,0#40   SET CPU PORT DISABLE BIT MASK
 EMP      SPACE  4,10
**        EMP - ENABLE MEMORY PORT.
*
*         ENTRY  (HBUF) = PROCESSOR INFORMATION.


          ROUTINE  EMP

          LOCKMR SET         ACQUIRE INTERLOCK
          LDM    S0EFLG      CHECK CPU TYPE
          NJP    EMP1        IF S0E

*         ENABLE MEMORY PORT FOR S0 PROCESSOR.

          LDDL   EC          SAVE REGISTER VALUE
          STDL   W0
          LDN    ECMR        *READMR RDATA,CMCC,ECMR*
          STDL   RN
          LDML   CMCC
          RJM    RMR         READ MAINTENANCE REGISTER
          LDM    RDATA       CLEAR BITS 3, 4
          LPC    0#E7
          STM    RDATA
          FUNCMR HBUF+CPRPC,MRMC   MASTER CLEAR THE PROCESSOR
          WRITMR RDATA       REWRITE *EC* REGISTER
          LDDL   W0          RESTORE *EC* DIRECT CELL
          STDL   EC
          LJM    EMP2        RELEASE INTERLOCK AND RETURN

*         ENABLE PAGE MAP PORT FOR S0E PROCESSOR.

 EMP1     LDM    HBUF+CPRPC  DETERMINE CPU NUMBER
          LPN    1
          STD    T1
          READMR RDATA,S0PMC,S0PPMC  READ PAGE MAP CONTROL REGISTER
          LDM    RDATA+1     CLEAR BIT 8 OR 9 DEPENDING ON CPU NUMBER
          LPML   EMPA,T1
          STM    RDATA+1
          FUNCMR HBUF+CPRPC,MRMC   MASTER CLEAR PROCESSOR
          WRITMR RDATA,S0PMC REWRITE PAGE MAP CONTROL REGISTER

*         COMMON EXIT.

 EMP2     LOCKMR CLEAR       RELEASE INTERLOCK
          LJM    EMPX        RETURN

 EMPA     CON    0#7F,0#BF   CLEAR CPU PORT DISABLE BIT MASK
 ENP      SPACE  4,10
**        ENP - ENABLE MEMORY PORT.
*
*         ENTRY  (HBUF) = PROCESSOR INFORMATION.
*
*         NOTE   THIS ROUTINE CONTAINS CODE FOR THE S0E WHICH IS SIMILAR TO THE
*                CODE IN *EMP* EXCEPT THAT THE PROCESSOR IS NOT MASTERCLEARED.
*                THIS ROUTINE SHOULD BE EXECUTED ON AN S0E MAINFRAME ONLY SINCE
*                IT DOES NOT CONTAIN CODE TO CORRECTLY ENABLE THE PORT ON AN S0.


          ROUTINE  ENP

          LOCKMR SET         ACQUIRE INTERLOCK

*         ENABLE PAGE MAP PORT FOR S0E PROCESSOR.

          LDM    HBUF+CPRPC  DETERMINE CPU NUMBER
          LPN    1
          STD    T1
          READMR RDATA,S0PMC,S0PPMC  READ PAGE MAP CONTROL REGISTER
          LDM    RDATA+1     CLEAR BIT 8 OR 9 DEPENDING ON CPU NUMBER
          LPML   ENPA,T1
          STM    RDATA+1
          WRITMR RDATA,S0PMC REWRITE PAGE MAP CONTROL REGISTER
          LOCKMR CLEAR       RELEASE INTERLOCK
          LJM    ENPX        RETURN

 ENPA     CON    0#7F,0#BF   CLEAR CPU PORT DISABLE BIT MASK

          OVERFLOW  10000    CHECK FOR OVERFLOW
          OVERLAY  (MASSAGE CPU REGISTERS)
*COPY CTP$DFT_MASSAGE_CPU_REGISTERS

          OVERFLOW  10000    CHECK FOR OVERFLOW
          OVERLAY  (CLEAR ERRORS)
 CLE      SPACE  4,10
**        CLE - CLEAR ERRORS.
*
*         EXIT   ALL REGISTERS NECESSARY WILL BE CLEARED OF ERRORS.


          ROUTINE  CLE

          LDM    HBUF+HDRPC
          STD    EC
          FUNCMR ,MRCE       CLEAR ERRORS FROM PAGE MAP REGISTERS
          LJM    CLEX        RETURN
 CPE      SPACE  4,10
**        CPE - CLEAR PAGE MAP ERRORS.
*
*         EXIT   ALL REGISTERS NECESSARY WILL BE CLEARED OF ERRORS.


          ROUTINE  CPE

          LDM    S0PMC       PAGE MAP CONNECT CODE
          STD    EC
          FUNCMR ,MRCE       CLEAR ERRORS FROM PAGE MAP REGISTERS
          LJM    CPEX        RETURN

          OVERFLOW  10000    CHECK FOR OVERFLOW
          OVERLAY  (DFT REQUEST PROCESSORS)
*COPY CTP$DFT_RETURN_ERROR_CODE
*COPYC CTP$DFT_OS_REQUESTS
*COPYC CTP$DFT_OS_REQUESTS_PACKETS

          OVERFLOW  10000    CHECK FOR OVERFLOW
          OVERLAY  (DFT REQUEST PROCESSORS - 2)
*COPY CTP$DFT_RETURN_ERROR_CODE
*COPYC CTP$DFT_REQUEST_PROCESSOR_2

          OVERFLOW  10000    CHECK FOR OVERFLOW
          OVERLAY  (PP REQUEST PROCESSORS)
*COPY CTP$DFT_RETURN_ERROR_CODE
*COPY CTP$DFT_PP_UTILITY_REQUESTS
*COPY DSI$930_DUMP_LOAD_IDLE_PP
*COPY CTP$DFT_930_DUMP_PP_REGS
 CIE      SUBR
          UJN    CIEX        STUB ON AN S0

          OVERFLOW  10000    CHECK FOR OVERFLOW
          OVERLAY  (ISSUE MONITOR TIMEOUT MESSAGE)
*COPY     CTP$DFT_UPDATE_170_MEMORY
          OVERFLOW  10000
          OVERLAY  (DFT ERROR LOGGING ROUTINES)
*COPY     CTP$DFT_PROCESS_DISK_ERROR
*COPY CTP$DFT_RETURN_ERROR_CODE

          OVERFLOW  10000
          OVERLAY  (DFT RUN TIME ERROR HANDLING)
*COPY CTP$DFT_RUN_TIME_ERROR_HANDLER
*COPY CTP$DFT_RETURN_ERROR_CODE
*COPY CTP$CONSTRUCT_MESSAGE_IN_EICB

          OVERFLOW  10000    CHECK FOR OVERFLOW
          END
/EOR
