          EJECT
*         CTEXT  CTP$DFT MASSAGE CPU REGISTERS.
*
*         THIS DECK CONTAINS ROUTINES THAT LOAD CPU REGISTERS
*         FOR INITIALIZATION, HALF EXCHANGE OPERATIONS, AND
*         HALTING OPERATIONS.
 HAP      SPACE  4,10
**        HAP - HALT ALL PROCESSORS.
*
*         CALLS  FHE, *STP*.


          ROUTINE HAP

          LDN    0           INITIALIZE ELEMENT ORDINAL
          STM    ELMO
          LDN    PROCID      SEARCH FOR NEXT PROCESSOR
 HAP1     RJM    FHE
          MJP    HAPX        IF ALL PROCESSORS HALTED
          CALL   STP         STOP PROCESSOR
          AOM    ELMO        GET NEXT ELEMENT
          SHN    14
          ADN    PROCID
          UJN    HAP1        LOOP
 IXP      SPACE  4,10
**        IXP - INITIALIZE EXCHANGE PACKAGE.
*
*         ENTRY  *MPS* REGISTER INITIALIZED IN PROCESSOR.
*
*         EXIT   MONITOR EXCHANGE PACKAGE INITIALIZED.
*
*         CALLS  PAC, SPB, *SRA*.


          ROUTINE IXP

          LDM    MPSR
          STD    RN
          READMR RDATA,HBUF+CPRPC  READ *MPS*
          RJM    PAC

*         CONVERT PACKED (8 BIT TO 16 BIT) FORMAT TO R-REGISTER FORMAT.

          LDML   MRVAL+2
          STDL   W2
          LDML   MRVAL+3
          STDL   W3
          CALL   SRA         CONVERT RMA BYTE ADDRESS TO R-POINTER
          RJM    SPB         SET PP BOUNDS
          LDDL   W6
          ADC    RR+1+0#1E
          CRDL   W0          FETCH *XE* REGISTER
          LDDL   W6
          ADC    RR+1+0#0D   GET BASE CONSTANT REGISTER
          CRDL   T4
          LDDL   W1          GET BASE VALUE FROM XE
          STDL   T4          INITIALIZE BASE CONSTANT REGISTER
          LDD    CP          GET CPU INDEX
          STD    T1
          ZJN    IXP6        IF CPU 0

*         CALCULATE BASE CONSTANT = BASE + SIZE * CPU INDEX.

 IXP5     LDDL   W3
          RADL   T4          ADD IN SIZE
          SOD    T1
          MJN    IXP5        IF NEED TO ADD MORE
 IXP6     LDDL   W6
          ADC    RR+1+0#0D
          CWDL   T4          REWRITE BASE CONSTANT
          LJM    IXPX        RETURN
 LCB      SPACE  4,10
**        LCB - LOAD CPU REGISTERS FROM BUFFER.
*
*         ENTRY  REGISTERS POINTED TO BY REQUEST.
*
*         EXIT   REGISTERS LOADED IN CPU.
*
*         CALLS  GNR, LRP, SRB.


          ROUTINE LCB        ENTRY/EXIT

          RJM    LRP         LOAD REQUEST POINTER
          CRDL   W0
          LDDL   W1          LOAD OFFSET TO BUFFER
          LRD    W2
          RJM    SRB         SET UP REGISTER BUFFER
 LCB1     RJM    GNR         GET NEXT REGISTER
          ZJP    LCBX        IF NO MORE REGISTERS TO PROCESS
          LDC    0#0800      INCLUDE TYPE-8 REGISTER FLAG FOR S0/S0E MAINFRAMES
          RAD    RN
          WRITMR RDATA,HBUF+CPRPC  LOAD REGISTER
          UJN    LCB1
 LCR      SPACE  4,10
**        LCR - LOAD CPU REGISTERS FROM BUFFER (CALL FORMAT REVISED FOR LVL 92).
*
*         ENTRY  REGISTERS POINTED TO BY REQUEST + 1.
*
*         EXIT   REGISTERS LOADED IN CPU.
*
*         USES   W0 - W4.
*
*         CALLS  GNR, LRP, SRB.


          ROUTINE  LCR       ENTRY/EXIT

          LDM    S0FLG       CHECK MAINFRAME TYPE
          ZJN    LCR1        IF NOT POSSIBLY DUAL-CPU S0E
          RJM    HOC         HALT OTHER CPU
 LCR1     RJM    LRP         LOAD REQUEST POINTER
          ADN    1
          CRDL   W0
          LDML   W3          SAVE LENGTH
          STML   LCRA
          LDDL   W0          LOAD OFFSET TO BUFFER
          LRD    W1
          RJM    SRB         SET UP REGISTER BUFFER
 LCR2     LDC    **          CHECK FOR LENGTH EXHAUSTED
 LCRA     EQU    *-1
          ZJN    LCR4        IF LENGTH HAS BEEN EXCEEDED
          RJM    GNR         GET NEXT REGISTER
          ZJN    LCR3        IF NO MORE REGISTERS TO PROCESS
          LDC    0#0800      INCLUDE TYPE-8 REGISTER FLAG FOR S0/S0E MAINFRAMES
          RAD    RN
          WRITMR RDATA,HBUF+CPRPC  LOAD REGISTER
          SOML   LCRA
          UJN    LCR2        GET NEXT REGISTER

 LCR3     LDM    S0FLG       CHECK MAINFRAME TYPE
          ZJP    LCRX        IF NOT POSSIBLY DUAL-CPU S0E
          RJM    SOC         START OTHER CPU
          LJM    LCRX        RETURN

*         DFT ANALYSIS - R POINTER LENGTH EXCEEDED.

 LCR4     SETDAN (EPUN,DADV)
          LDC    DADV+TDFT   619 -- R-POINTER LENGTH EXCEEDED IN *DVR* PROCESSING
          STML   RTP1
          CALL   ERRH        ISSUE MESSAGE AND HANG
 PRI      SPACE  4,10
**        PRI - PREPARE FOR REGISTER INITIALIZATION.
*
*         PROCESSOR IS MASTER CLEARED, *CSA* REGISTER IS SET TO IDLE,
*         AND PROCESSOR RESTARTED.
*
*         ENTRY  PROCESSOR IS HALTED.
*
*         EXIT   PROCESSOR IS READY FOR REGISTER INITIALIZATION.
*
*         CALLS  SMC, *EMP*.


          ROUTINE PRI

          CALL   EMP         CLEAR PORT DISABLE FOR PROCESSOR
          CALL   CLE         CLEAR ERRORS IN THE CPU BEFORE INITIALIZATION
          LDD    MD          GET MODEL
          SHN    -4
          LMN    2
          NJN    PRI0        IF NOT AN 835
          LDML   MLIT        LONG INIT ADDRESS
          UJN    PRI1

 PRI0     LDML   MIDL
          STDL   T1
          LMC    4000        NULL MICROCODE ADDRESS
          ZJN    PRI2        IF NO MICROCODE ROUTINE NEEDED
          LDDL   T1
 PRI1     RJM    SMC         START MICROCODE
 PRI2     LJM    PRIX        RETURN
 SCR      SPACE  4,10
**        SCR - SAVE CPU REGISTERS.
*
*         THE CPU REGISTERS ARE SAVED IN A BUFFER PROVIDED IN THE
*         CALL TO DFT.
*
*         ENTRY  NOS/VE REQUEST CONTAINS BUFFER ADDRESS.
*
*         EXIT   APPROPRIATE REGISTERS ARE SAVED.
*
*         CALLS  LRP, SNR, SPB, SRB.


          ROUTINE SCR        ENTRY/EXIT

          RJM    LRP         LOAD REQUEST POINTER
          CRDL   W0          FETCH REQUEST
          LRD    W2
          RJM    SPB         SET PP BOUNDARY
          LDC    SCRB        *H1P* REGISTER LIST
          STD    T6
          LDD    JT+3
          SBN    H1P
          ZJN    SCR1        IF *H1P* HALT 170 PROCESSOR
          LDC    SCRA        REGISTER LIST FOR ALL OTHERS
          STD    T6
          LDD    CP          FORM OFFSET TO REGISTER LIST (CP * 16)
          SHN    4
 SCR1     ADDL   W1          ADD OFFSET TO BUFFER
          RJM    SRB         SET UP REGISTER BUFFER
 SCR2     LDI    T6
          STD    RN          SAVE REGISTER NUMBER
          ZJP    SCRX        IF END OF REGISTERS
          READMR RDATA       READ REGISTER CONTENTS
          RJM    SNR         STORE NEXT REGISTER
          AOD    T6
          UJN    SCR2        READ NEXT REGISTER

*         REGISTER SAVE LISTS USED FOR DUAL STATE SWITCHING.

 SCRA     CON    PPRG        PROGRAM REGISTER
          CON    PUPR        UNTRANSLATABLE POINTER

*         NOTE: THE ORDER IN THE FOLLOWING REGISTER LIST IS IMPORTANT.
*         *PTL* AND *PSM* SHOULD BE SET UP BEFORE *PTA* IS INITIALIZED.
*         BOGUS VALUES IN THE *PTA* REGISTER WILL RESULT IF THIS ORDER IS
*         NOT FOLLOWED.

 SCRB     CON    PPTL        PAGE TABLE LENGTH
          CON    PPSM        PAGE SIZE MASK
          CON    PPTA        PAGE TABLE ADDRESS
          CON    PSIT        PROCESSOR SIT
          CON    PMPS        MONITOR PROCESS POINTER
          CON    PJPS        JOB PROCESS POINTER
          CON    0           END OF TABLE
 SMP      SPACE  4,10
**        SMP - SET *MPS* REGISTER IN PROCESSOR (CALL REVISED FOR LVL 92).
*
*         ENTRY  *MPS* VALUE IN NOS/VE REQUEST.
*
*         USES   RN, W0 - W3.
*
*         CALLS  LRP, UPR.
*
*         MACROS WRITMR.


          ROUTINE  SMP

          RJM    LRP         LOAD REQUEST POINTER
          CRDL   W0          FETCH PARAMETER WITH *MPS*
          LDDL   W2
          STML   MRVAL+2
          LDDL   W3
          STML   MRVAL+3
          RJM    UPR         UNPACK REGISTER
          LDM    MPSR
          STD    RN
          WRITMR RDATA,HBUF+HDRPC
          LJM    SMPX        RETURN
 SMR      SPACE  4,10
**        SMR - SET *MPS* REGISTER IN PROCESSOR.
*
*         ENTRY  *MPS* VALUE IN NOS/VE REQUEST.
*
*         USES   W0 - W3.
*
*         CALLS  UPR.


          ROUTINE SMR

          RJM    LRP
          ADN    1
          CRDL   W0          FETCH PARAMETER WITH *MPS*
          LDDL   W2
          STML   MRVAL+2
          LDDL   W3
          STML   MRVAL+3
          RJM    UPR         UNPACK REGISTER
          LDM    MPSR
          STD    RN
          WRITMR RDATA,HBUF+HDRPC
          LJM    SMRX        RETURN
 SRA      SPACE  4,10
**        SRA - SET RELOCATION ADDRESS.
*
*         ENTRY  (MRVAL) = PACKED REGISTER 32 BIT RMA BYTE ADDRESS.
*
*         EXIT   (A) = PARTIAL ADDRESS.
*                (W6) = PARTIAL ADDRESS.
*                THE INPUT BYTE ADDRESS RMA WILL BE CONVERTED TO
*                AN R-REGISTER POINTER WORD ADDRESS.
*
*         CALLS  STA.


          ROUTINE SRA

          LDN    2
          STD    T5
          LDN    3
          STD    T6
          LDML   MRVAL,T5
          STDL   W2
          LDML   MRVAL,T6
          SHN    -3
          STDL   W3
          LDDL   W2
          LPN    7
          SHN    15
          LMDL   W3
          STDL   W3
          LDDL   W2
          SHN    -3
          STDL   W2
          RJM    STA
          LJM    SRAX        RETURN
 STP      SPACE  4,10
**        STP - STOP PROCESSOR.
*
*         CALLS  RMR, *ERRH*.


          ROUTINE STP

          LDM    HBUF+CPRPC  CHECK PORT CODE
          ZJN    STP3        IF INVALID PORT
          LDN    SSMR
          STD    RN
          LDM    HBUF+CPRPC
          RJM    RMR         READ SUMMARY STATUS
          LPN    0#8
          NJN    STP2        IF PROCESSOR IS HALTED
          FUNCMR ,MRHP       STOP PROCESSOR
 STP2     LDM    HBUF+CPRPC
          RJM    RMR         READ SUMMARY STATUS
          LPN    0#8
          ZJN    STP2        IF NOT HALTED
          LJM    STPX        RETURN

*         DFT ANALYSIS - INVALID PORT CODE FOR CPU.

 STP3     SETDAN (EPUN,DADV)
          LDC    DAHP+TDFT   609 - DFT HALT PROCESSOR
          STML   RTP1
          CALL   ERRH        ISSUE MESSAGE AND HANG
 HOC      SPACE  4,10
**        HOC - HALT OTHER CPU.
*
*         ON DUAL-CPU S0E MAINFRAMES, THE SHARED PAGE MAP ELEMENT REQUIRES
*         THAT NEITHER CPU BE ACTIVE WHEN INITIALIZING *PTA*, *PTL*, OR *PSM*
*         IN EITHER CPU.
*
*         NOTE   THIS ROUTINE ASSUMES THAT NO MORE THAN TWO CPUS EXIST.
*                THE CONTENTS OF *HBUF* MUST NOT BE DISTURBED.
*
*         MACROS FUNCMR, READMR.


 HOC      SUBR               ENTRY/EXIT
          READMR RDATA,S0PMC,S0PPMC  GET CPU PORT ENABLE/DISABLE STATUS
          LDM    HBUF+CPRPC  DETERMINE CPU NUMBER BEING INITIALIZED
          LPN    1
          ZJN    HOC1        IF CPU-0 BEING INITIALIZED

*         HALT CPU-0 IF PRESENT AND ACTIVE.

          LDM    CPU0M       CHECK IF CPU-0 PRESENT
          ZJN    HOCX        IF CPU-0 NOT PRESENT
          LDM    RDATA+1     CHECK CPU-0 ENABLE/DISABLE STATUS
          LPC    0#80
          NJN    HOCX        IF CPU-0 NOT ENABLED
          FUNCMR CP0CC,MRHP  HALT CPU-0
          LJM    HOCX        RETURN

*         HALT CPU-1 IF PRESENT AND ACTIVE.

 HOC1     LDM    CPU1M       CHECK IF CPU-1 PRESENT
          ZJN    HOC2        IF CPU-1 NOT PRESENT
          LDM    RDATA+1     CHECK CPU-1 ENABLE/DISABLE STATUS
          LPC    0#40
          NJN    HOC2        IF CPU-1 NOT ENABLED
          FUNCMR CP1CC,MRHP  HALT CPU-1
 HOC2     LJM    HOCX        RETURN
 SOC      SPACE  4,10
**        SOC - START OTHER CPU.
*
*         ON DUAL-CPU S0E MAINFRAMES, THE SHARED PAGE MAP ELEMENT REQUIRES
*         THAT NEITHER CPU BE ACTIVE WHEN INITIALIZING *PTA*, *PTL*, OR *PSM*
*         IN EITHER CPU.
*
*         NOTE   THIS ROUTINE ASSUMES THAT NO MORE THAN TWO CPUS EXIST.
*                THE CONTENTS OF *HBUF* MUST NOT BE DISTURBED.
*
*         MACROS FUNCMR, READMR.


 SOC      SUBR               ENTRY/EXIT
          READMR RDATA,S0PMC,S0PPMC  GET CPU PORT ENABLE/DISABLE STATUS
          LDM    HBUF+CPRPC  DETERMINE CPU NUMBER BEING INITIALIZED
          LPN    1
          ZJN    SOC1        IF CPU-0 BEING INITIALIZED

*         START CPU-0 IF PRESENT AND ACTIVE.

          LDM    CPU0M       CHECK IF CPU-0 PRESENT
          ZJN    SOCX        IF CPU-0 NOT PRESENT
          LDM    RDATA+1     CHECK CPU-0 ENABLE/DISABLE STATUS
          LPC    0#80
          NJN    SOCX        IF CPU-0 NOT ENABLED
          FUNCMR CP0CC,MRSP  START CPU-0
          LJM    SOCX        RETURN

*         START CPU-1 IF PRESENT AND ACTIVE.

 SOC1     LDM    CPU1M       CHECK IF CPU-1 PRESENT
          ZJN    SOC2        IF CPU-1 NOT PRESENT
          LDM    RDATA+1     CHECK CPU-1 ENABLE/DISABLE STATUS
          LPC    0#40
          NJN    SOC2        IF CPU-1 NOT ENABLED
          FUNCMR CP1CC,MRSP  START CPU-1
 SOC2     LJM    SOCX        RETURN
 COMMON   SPACE  4,10
*         COMMON DECKS.


 QUAL$    EQU    0           DEFINE UNQUALIFIED COMMON DECK
*COPY     CTP$DFT_START_MICROCODE

*         END    CTP$DFT MASSAGE CPU REGISTERS
