          EJECT
*         CTEXT  CTP$DFT PROCESSOR PRIMITIVES.
*
*         THIS DECK PROVIDES CPU PRIMITIVES WHICH ENABLE
*         HALTING, STARTING, AND HALF EXCHANGE OPERATIONS ON
*         A CPU.
 DCP      SPACE  4,10
**        DCP - DISABLE CPU.
*
*         PERFORMS CALLS TO ROUTINES WHICH ULTIMATELY DISABLE
*         THE CPU.
*
*         CALLS  *DMP*, *HEO*, *HPR*, *IDL*, *SCR*.


          ROUTINE  DCP

          CALL   HPR         HALT PROCESSOR
          CALL   HEO         HALF EXCHANGE OUT
          CALL   IDL         IDLE MICROCODE
          CALL   SCR         SAVE CPU REGISTERS
          CALL   DMP         DISABLE MEMORY PORT
          LJM    DCPX        RETURN
 HEI      SPACE  4,10
**        HEI  - HALF-EXCHANGE IN TO START PROCESSOR.
*
*         ENTRY  PROCESSOR MASTER CLEARED, *CSA* REGISTER SET TO (STEX)
*                *BLOCK EXCHANGE REQUEST* AND *DISABLE PROCESSOR FAULT
*                STATUS* BITS ARE CLEARED IN *DEC*, PROCESSOR STARTED
*                AND THE DEADSTART INTERLOCK IS CLEARED IN THE *EICB*.
*
*         EXIT   PROCESSOR HALF EXCHANGED OUT TO MONITOR
*                EXCHANGE PACKAGE AT *MPS*.
*
*         CALLS  CLRBTS.


          ROUTINE  HEI

*         START THE PROCESSOR.

          LDML   HEIM        GET HALF EXCHANGE IN ADDRESS
          STM    HEIB+7
          SHN    -8D
          STM    HEIB+6
          LOCKMR SET
          FUNCMR HBUF+CPRPC,MRMC   MASTER CLEAR PROCESSOR
          RJM    CLRBTS      CLEAR MODEL-DEPENDENT *DEC* BITS
          LDML   CSAR
          STDL   RN
          WRITMR HEIB,HBUF+CPRPC
          FUNCMR HBUF+CPRPC,MRSP   START PROCESSOR
          LDC    200D        WAIT 100 MICRO SECS
 HEI1     SBN    1
          NJN    HEI1        DELAY

*         CLEAR  MAINTENANCE REGISTER INTERLOCK.

          LOCKMR CLEAR
          LJM    HEIX        RETURN

 HEIB     BSSZ   10          CONTROL STORE ADDRESS
 HEO      SPACE  4,10
**        HEO - HALF EXCHANGE OUT.
*
*         THE CURRENTLY ACTIVE EXCHANGE PACKAGE IS SAVED WITHIN
*         THE EXCHANGE PACKAGE SAVE AREA IN REAL MEMORY.
*
*         ENTRY  PROCESSOR HALTED.
*
*         EXIT   EXCHANGE PACKAGE SAVED IN REAL MEMORY.
*
*         CALLS  RMR, SMC.


          ROUTINE  HEO

          LDN    SSMR
          STD    RN
          LDM    HBUF+CPRPC
          RJM    RMR         READ PROCESSOR SUMMARY STATUS
          LPN    0#20
          ZJN    HEO1        IF PROCESSOR IN JOB MODE
          LDML   HEOM        HALF EXCHANGE OUT MONITOR ADDRESS
          UJN    HEO2        DO EXCHANGE

 HEO1     LDML   HEOJ        HALF EXCHANGE OUT JOB ADDRESS
 HEO2     RJM    SMC         START MICROCODE
 HEO3     LDN    SSMR
          STD    RN
          LDD    EC
          RJM    RMR         READ PROCESSOR SUMMARY STATUS
          LPN    0#8
          ZJN    HEO3        IF PROCESSOR NOT HALTED
          LJM    HEOX        RETURN
 HPR      SPACE  4,10
**        HPR - HALT PROCESSOR.
*
*         PROCESSOR IS HALTED, THE *DISABLE PROCESSOR FAULT
*         STATUS* AND THE *BLOCK EXCHANGE REQUEST* BITS ARE SET
*         IN THE *DEC* REGISTER.
*
*         CALLS  RMR, *ERRH*, *STRBTS*.


          ROUTINE  HPR

          LDM    HBUF+CPRPC  CHECK PORT CODE
          ZJP    HPR4        IF INVALID PORT
          LDM    HBUF+CPRE+EM
          SHN    -4
          STD    MD          SET UP MODEL TYPE
          LDN    SSMR
          STD    RN
          LDM    HBUF+CPRPC
          RJM    RMR         READ SUMMARY STATUS
          LPN    0#8
          NJN    HPR2        IF PROCESSOR IS HALTED
          FUNCMR ,MRHP       STOP PROCESSOR
 HPR2     LDM    HBUF+CPRPC
          RJM    RMR         READ SUMMARY STATUS
          LPN    0#8
          ZJN    HPR2        IF NOT HALTED

*         PREPARE THE *DEC* REGISTER FOR MODEL-DEPENDENT
*         HALF EXCHANGE OPERATIONS.

 HPR3     READMR RDATA,,DEMR READ *DEC* REGISTER
          CALL   STRBTS      SET BITS IN *DEC*
          WRITMR RDATA       REWRITE *DEC* REGISTER
          LJM    HPRX        RETURN

 HPR4     SETDAN (EPUN,DAHP)
          LDC    DAHP+TDFT   609 - DFT HALT PROCESSOR
          STML   RTP1
          CALL   ERRH        ISSUE MESSAGE AND HANG
 IDL      SPACE  4,10
**        IDL - DEADSTART PROCESSOR TO IDLE ADDRESS.
*
*         PROCESSOR IS MASTER CLEARED, *CSA* REGISTER IS SET TO *IDLE*
*         AND PROCESSOR IS STARTED.
*
*         ENTRY  PROCESSOR IS HALTED.
*
*         EXIT   PROCESSOR IS READY FOR REGISTER DUMP.
*
*         USES   T1.
*
*         CALLS  SMC.


          ROUTINE  IDL

          LDML   MIDL
          STDL   T1
          LMC    4000        NULL MICROCODE ADDRESS
          ZJP    IDLX        IF NO MICROCODE NEEDED
          LDDL   T1
          RJM    SMC         START MICROCODE
          LJM    IDLX        RETURN
 PCP      SPACE  4,10
**        PCP - PROCESS CPU.
*
*         EXIT   VE REQUEST UPDATED WITH NUMBER OF FIRST ACTIVE CPU.
*
*         CALLS  CMP, FHE, *DCP*.


          ROUTINE  PCP

          READMR RDATA,CMCC,ECMR
          LDN    0
          STD    CP          CPU ORDINAL
 PCP1     LDD    CP
          SHN    14
          ADN    PROCID
          RJM    FHE         FIND HARDWARE DATA ON SELECTED CPU
          MJP    PCPX        IF THRU WITH ALL CPUS
          LDM    HBUF+CPRSTAT+PSCPOFF
          LPC    1001
          NJN    PCP3        IF CPU OFF OR DOWN
          RJM    CMP
          NJN    PCP3        IF PORT DISABLED
          CALL   DCP         PERFORM STEPS TO DISABLE THIS CPU
 PCP3     AOD    CP
          LDN    EICBP       SCI IS TAKING VE DOWN, SO WE HAVE
          CRDL   CM          SEE IF THIS IS A DUAL CPU, NOS SYSTEM
          LDDL   CM          WITH NOS IN CPU-1.  CHECK WORD 71
          LPC    0#0480      BITS 5 AND 8.  IF SET, THEN LEAVE
          LMC    0#0480      CPU-1 ALONE, AND CLEAR BIT 8.
          NJN    PCP1        NOT DUAL NOS SYSTEM
          LRD    IB+1        SET UP TO GET BOUNDS TO LOWER
          RJM    SPB         SET THE BOUNDS REG
          LDC    0#FF7F      SET UP TO CLEAR BIT 8
          STDL   CM
          LCN    0
          STDL   CM+1
          STDL   CM+2
          STDL   CM+3
          LDN    EICBP       RE-WRITE WORD 71
          RDCL   CM
          LJM    PCPX        DO NOT PROCESS CPU-1
 SAP      SPACE  4,10
**        SAP - START ALL PROCESSORS.
*
*         EXIT   ALL PROCESSORS IN MAINFRAME WILL BE STARTED.
*
*         CALLS  FHE, *SPR*.


          ROUTINE  SAP

          LDN    0
          STM    ELMO        ELEMENT ORDINAL
          LDN    PROCID
 SAP1     RJM    FHE
          MJP    SAPX        IF ALL PROCESSORS STARTED
          RJM    CMP         CHECK MEMORY PORT
          NJN    SAP2        IF PORT DISABLED
          CALL   SPR         CALL START PROCESSOR
 SAP2     AOM    ELMO        GET NEXT ELEMENT
          SHN    14
          ADN    PROCID
          UJN    SAP1        LOOP
 SPR      SPACE  4,10
**        SPR - START PROCESSOR.


          ROUTINE  SPR

          FUNCMR HBUF+CPRPC,MRSP
          LJM    SPRX        RETURN

**        SB8 - SET BIT 8 OF WORD 71 IF BIT 5 IS SET
*
*         THIS ROUTINE IS CALLED DURING A DUAL STATE
*         DEADSTART OF NVE.  IF CM WORD 71, BIT 5 IS
*         SET, THEN THIS IS A DUAL STATE TRANSITION
*         TO CPU-0 ONLY.  BIT 8 MUST BE SET BEFORE
*         CPU-0 IS STARTED, SO THAT NVE WILL HANDLE
*         ALL INTERRUPTS.  THE MICROCODE WILL KEY ON
*         THAT BIT ALSO, TO PASS ALL INTERRUPTS UP.

          ROUTINE   SB8

          LDN    EICBP       READ WORD 71
          CRDL   T1
          LDDL   T1
          SHN    21-12
          PJP    SB8X        BIT 5 NOT SET
          LRD    IB+1        SET THIS PP TO BELOW BOUNDS
          RJM    SPB
          LDC    0#80        SET BIT 8 IN MASK
          STDL   T1
          LDN    0
          STD    T1+1
          STD    T1+2
          STD    T1+3
          LDN    EICBP       SET THE BIT
          RDSL   T1
          UJP    SB8X        EXIT

 COMMON   SPACE  4,10
*         COMMON DECKS.


 QUAL$    EQU    0           DEFINE UNQUALIFIED COMMON DECK
*COPY     CTP$DFT_START_MICROCODE

*         END    CTP$DFT PROCESSOR PRIMITIVES
