          CTEXT  CTP$DFT RELEASE HISTORY.
 HISTORY  SPACE  4,10
***       *DFT* RELEASE HISTORY.
*
*         LEVEL 01 - RELEASED WITH CIP005 AND NOS/VE 1.1.4, SEPT. 1985.
*
*         LEVEL 99 - CONTAINED CYBER 810 FIX.
*
*         LEVEL 02 - RELEASED WITH CIP006 AND NOS/VE 1.2.1, AUG. 1986.
*
*         LEVEL 98 - CONTAINED I4 CHANNEL STATUS FIX.
*
*         LEVEL 97 - CONTAINED SEVERAL PSR FIXES, REMOVED TIMEOUT ON
*         ACQUIRING CH17 FLAG, CORRECTED CH17 ERROR HANDLING, AND ADDED
*         SUPPORT FOR 840S MAINFRAME.
*
*         LEVEL 96 - CONTAINED TWO PSR FIXES.
*
*         LEVEL 95 - CONTAINED THREE THETA-RELATED PSR FIXES.
*
*         LEVEL 03 - RELEASED WITH CIP007 AND NOS/VE 1.2.2, APRIL 1987.
*
*         LEVEL 94 - CONTAINED SEVERAL PSR FIXES.  RELEASED JUNE 1987.
*
*         LEVEL 93 - RELEASED WITH CIP008 AND NOS/VE 1.2.3, SEPT. 1987.
*
*         LEVEL 92 - CONTAINED LRZ DUAL I4 PRE-RELEASE CODE, OCT. 1987.
*
*         LEVEL 04 - RELEASED WITH CIP009 AND NOS/VE 1.3.1, APRIL 1988.
*         IN THIS RELEASE DFT WAS SPLIT INTO MODEL-SPECIFIC VARIANTS FOR
*         LOWER CYBER 8XX, CYBER 835, UPPER CYBER 8XX, CYBER 930, CYBER 960,
*         AND CYBER 990.
*
*         LEVEL 89 - CODE REVISION 89 WAS NEVER FIELD RELEASED.  CHANGES
*         INCLUDE SUPPORT FOR ENHANCED I4 PACKETS AND USE OF A COMMON
*         DECK FOR GENERATING FAULT SYMPTOM CODES FOR MEMORY ERRORS
*         ON A CYBER 960.
*
*         LEVEL 88 - RELEASED WITH CIP LEVEL 704, JUNE 1988. CHANGES INCLUDE
*         SUPPORT FOR THE CYBER 960 SERIES HARDWARE.
*
*         LEVEL 87 - RELEASED WITH CIP LEVEL 710, SEP. 1988. CONTAINED FIX
*         FOR A CYBER 960 HARDWARE DEFICIENCY.
*
*         LEVEL 86 - CONTAINED FIX FOR A CYBER 960 PROBELM INVOLVING THE
*         MAC. RELEASED DEC. 1988.
*
*         LEVEL 05 - RELEASED WITH CIP LEVEL 716, DECEMBER, 1988.
*
*         LEVEL 85 - ADDED CAPABILITY TO HANDLE CPU DEADMAN TIMEOUT FROM
*         CENTRAL MEMORY REFERENCE ON 96X. RELEASED JAN. 1989.
*
*         LEVEL 84 - CONTAINED FIX FOR NV05819 IN WHICH DFT PRESET WAS
*         CORRUPTING A WORD IN CENTRAL MEMORY. RELEASED FEB. 1989.
*
*         LEVEL 83 - ADDED DUAL 960 CPU SUPPORT TO DFT.
*
*         LEVEL 82 - CONTAINED A FIX FOR DFTA184 (960 DFT VARIANT).
*         THIS FIX RESTARTS A 960 CPU WHEN IT IS HALTED AND NO
*         CORRECTED OR UNCORRECTED ERRORS ARE PRESENT AND THE MICRAND
*         ADDRESS IS 5.  RELEASED MARCH, 1989.
*
*         LEVEL 06 - ADDED SUPPORT FOR THE SECONDARY DFT POINTER IN THE
*         DFT BUFFER AREA. RELEASED WITH CIP LEVEL 727, JUNE, 1989.
*
*         LEVEL 07 - ADDED SUPPORT FOR DFT TO PUT 1707, 1708, 4XX, 5XX, 6XX
*         AND NEGATIVE SIT ANALYSIS CODES IN THE NON-REGISTER STATUS BUFFER.
*         RELEASED WITH CIP LEVEL 739 DECEMBER, 1989.
*
*         LEVEL 81 - ADDED FIXES FOR: HAVING A 960 WITHOUT A PC CONSOLE,
*         DFT INTERNAL KNOWLEDGE OF WHETHER IT IS AN UPPER OR LOWER PP, AND
*         IGNORING A BAD PACKET STATUS FROM THE PC CONSOLE ON A 930 DOING
*         A DATE/TIME UPDATE. RELEASED IN FEBRUARY, 1990.
*
*         LEVEL 08 - SAME AS LEVEL 81, RELEASED WITH CIP LEVEL 750, JUNE, 1990.
*
*         LEVEL 80 - SUPPORTED RELOAD OF SCM ON THETA MODELS AT TOP OF HOUR.
*
*         LEVEL 80 - SUPPORTED NOT HALTING CPU WHEN IN STANDALONE NOS ON THE 960
*                    AND CHANGING MEMORY REGISTERS.
*
*         LEVEL 79 - CHANGES FOR 990, 960, 830 TO UPDATE MRT ON CIP DISK WHEN
*                    IN STANDALONE VE.
*
*         LEVEL 09 - SUPPORTS LEVEL 1.5.3 CIP L765.
*
*         LEVEL 10 - SUPPORTS LEVEL 1.6.1 CIP L780.
*
*         LEVEL 11 - SUPPORTS LEVEL 780AB.
*
*         LEVEL 12 - CONTAINED A FIX FOR 960 VARIANT OF DFT TO RESOLVE
*         PSR DFT0055.  RELEASED APRIL, 1992.
*
*         LEVEL 13 - CONTAINED A FIX FOR 960 VARIANT OF DFT TO RESOLVE
*         PSR DFTA213 (ALSO INCLUDED DFT0055 FIX).  RELEASED JUNE, 1992.
*
*         LEVEL 14 - FIX TO WAIT 100MS AFTER HALT PROCESSOR
*
*         LEVEL 15 - CHANGES TO 960 VARIANT TO IMPLEMENT DUAL STATE
*         NOS/NOSVE IN CPU-0, AND NOS ONLY IN CPU-1.  DFT WILL TEST
*         WORD 71, BIT 5 (NOS IN BOTH CPU-S) FLAG DURING A DUAL-STATE
*         DEADSTART CALL FROM SCI.  IF SET, THEN DFT SETS BIT 8 IN THAT
*         WORD SO THAT THE 960 MICROCODE WILL PASS CPU-0 PURGE REQUESTS TO
*         NVE TRAP HANDLER, INSTEAD OF HAVING THE MICROCODE HANDLE IT.
*         DFT WILL CLEAR BIT 8 WHEN SCI TAKES NVE DOWN, SO THAT DUAL
*         CPU NOS CAN RESUME.  ALSO, DFT WILL NOT RESET PIT IN CPU-0
*         IF IT FINDS NVE FIELD LENGTH IN THE DUAL-STATE CONTROL BLOCK.
*         NOS USES PIT IN THAT MODE.

          SPACE  4,10
          ENDX
