          EJECT
*         CTEXT  CTP$DFT_RESET_PIT.
*
*         COMMENT  COPYRIGHT CONTROL DATA SYSTEMS INC. 1992
 RPT      SPACE  4,10
**        RPT - RESET PROCESS INTERVAL TIMER.
*
*         USES   T1 - T4, T7.
*
*         CALLS  RMR.
*
*         MACROS WRITMR.


 RPT      SUBR               ENTRY/EXIT
          LDN    EICBP       CHECK FOR PRESENCE OF DUAL CPU NOS
          CRDL   T1
          LDDL   T1
          SHN    21-12
          PJN    RPTX        IF NOT DUAL CPU NOS
          LDM    IOUN
          ZJN    RPT3        IF RUNNING IN IOU0
 RPT2     UJN    RPTX

*         INITIALIZE FOR PROCESSING ALL CPU-S.

 RPT3     LDN    ECMR        *READMR  RDATA,CMCC,ECMR*
          STDL   RN
          LDM    CMCC
          RJM    RMR         READ MAINTENANCE REGISTER
          LDM    RDATA,PO    SAVE PORT INFORMATION
          STM    RPTB
          LDN    2           NUMBER OF CPU-S TO PROCESS
          STM    RPTD
          LDC    PPIT        *PIT* REGISTER NUMBER
          STDL   RN

*         CHECK IF NEXT CPU IS TO BE PROCESSED.

 RPT4     SOML   RPTD
 RPT4A    MJN    RPT2        IF ALL CPU-S HAVE BEEN CHECKED
          STM    CPUO        SAVE CPU ORDINAL BEING EXAMINED
          STD    T7
          SHN    2
          RAD    T7
          ERRNZ  CPNR-5      CODE ASSUMES VALUE
          LDML   TCPU+CPUM,T7
          ZJN    RPT4        IF CPU NOT PRESENT
          LDC    SHNI+4+3
          SBM    TCPU+CPUP,T7
          STM    RPTA
          LDN    1
 RPTA     SHN    **
          STM    RPTC
          LDC    **
 RPTB     EQU    *-1
          LPC    **
 RPTC     EQU    *-1
          NJN    RPT4        IF PORT DISABLED

*         RESET *PIT*.
*         THE *PIT* WILL BE SET TO ALL ONES.

          LDC    0#FF
          STM    RDATA+4
          STM    RDATA+5
          STM    RDATA+6
          STM    RDATA+7
          LDM    TCPU+CPUC,T7
          STD    EC
          WRITMR RDATA
          LDN    D7CM        CHECK IF DUAL STATE IS CAPABLE
          RJM    IIB
          CRDL   T1          IN CPU-0.  IF SO, DO NOT RESET
          LDDL   T1+2        PIT IN CPU-0
          LPC    0#FF        ISOLATE 23-16 OF NVE CM LENGTH
          NJP    RPTX        NON-ZERO MEANS VE CAPABLE
          LDDL   T1+3        TEST THE REST OF NVE CM LENGTH
          NJP    RPTX        VE CAPABLE, NOS IS USING PIT
          LJM    RPT4        CONTINUE WITH NEXT PROCESSOR

 RPTD     BSS    1           NUMBER OF CPU-S TO PROCESS

*         ENDX   CTP$DFT_RESET_PIT.

