
MODULE mlm$memory_link_monitor_mode;
*copyc OSD$DEFAULT_PRAGMATS
{
{ the purpose of this module is to define memory link
{ structures in the mainframe wired segment.
{
?? PUSH (LISTEXT := ON) ??
*copyc MLD$MEMORY_LINK_DECLARATIONS
*copyc MLT$ANT_ENTRY
*copyc TMT$RB_READY_TASK
?? POP ??
*copyc MLT$C170_RQST_BLK

  VAR
    mlv$c170_rqst_blk: [XDCL, #GATE] mlt$c170_rqst_blk := [[REP mlimi of [idle,
      0, 0, 0, 0, 0, [REP 14 of 0]]], NIL, NIL, mlc$max_message_length + 1,
      reject_all_calls],
    mlv$enabled: [XDCL, #GATE] boolean := FALSE,
    mlv$enable_hot_key: [XDCL, #GATE] boolean := FALSE,
    mlv$debug: [XDCL, #GATE] boolean := FALSE,
    mlv$170_count: [XDCL, #GATE] integer := 0,
    mlv$170_time: [XDCL, #GATE] integer := 0,
    mlv$rb_ready_task: [XDCL, #GATE] tmt$rb_ready_task := [0, [TRUE, 0], [0, 0]];

MODEND mlm$memory_link_monitor_mode
