.PH "''''''"
.DF
                                               January 17, 1986










Greg Spac
QCI
2680 North First Street
Suite 204
San Jose, CA  95134


.DE

This is the spec that I would like to add to the 2K x 8, 4K x 4 and 16K x 4
25ns SRAM specs.  It involves the write cycle #1.

When write enable is pulled high while chip enable remains low, the data
driven by the SRAM will be the same data that was just written, provided
that the address lines remain stable.  This prevents a driver conflict
between the SRAM and the data driver when write enable is pulled high
to end the write cycle.

.DF
Thank you,



Rob Horning
Information Hardware Operation
Hewlett Packard
3404 East Harmony Road
Fort Collins, Colorado  80525

303 226-3800 x2501
.DE
