
Following are questions we would like answered concerning Cypress
static RAM's.  We are primarily interested in 4K x 4, 2K x 8, and any future
plans for SRAM's that are bigger or faster.

.H 1 "Timing"

Our timing is very tight and so we want to make sure that we simulate
everything as closely as possible.  We want to be conservative but we
we want to take advantage of every nano-second available.

Do you have any suggestions on how changing the load from a lumped RC
load (test circuit) to a transmission line (typical application) effects
the timing?  I have attached some scope outputs from the CY7C168-25.

What is the effect of ringing on address, enable and write lines?
If a signal rings below a 2 volts on a low to high transition or
above .8 volts on a high to low transition does the timing start from
the last point it started ringing?  Does this cause additional problems
on write strobe?  Some typical signals are shown below.
.DF











.DE

.H 1 "Failures"

What is the current failure rate that you see?  If it needs to be improved
what are you doing to improve it and what do you expect it to be in the future?
What are the failure modes?  What ones are most common?

Do you have any data yet on soft error rate?  When will you have the data?
Do you have any idea what it might be?

.H 1 "Future Parts"

What speeds and organizations are you planning on over the next couple of
years?  Do you have any ideas on the pinout?  Will there be industry standard
pinouts?  How do you expect the power requirements to change relative to
the current parts?  Do you expect errors rates to become a bigger problem?

.H 1 "Bus Contention"

What is the effect of having two parts enabled at the same time?

