
.DF
From: Rob Horning                                  Date: May 6,1985

  To: Craig Robinson                            Subject: Cypress
      Russ Sparks

  cc: Mark Forsyth
      Rick Luebs
      Ed Holland
      Tarang Patil
      Darius Tanksavala

.DE

This is a summary of what what was discussed when I went to Cypress last
week.

.H 1 "Cypress"

I went to Cypress knowing that they were doing a lot of things right.  I talked
to a couple of people who had visited them and both gave very favorable
reports.  Two words that they used a lot were fast and quality.  They want to
have the worlds fastest parts and they want the highest quality parts.
They were very proud of some of the things that they were doing to improve
quality.

Something new that I learned was that they do not have an objective to 
compete in mass markets.  They do not plan on getting into price wars with
Japan.  When a part gets to the point that everybody can make as many as the
market will buy they may stop making the part.  This makes it important that
we not depend on special Cypress features and try to work with some common
spec.  We need to work with MTC to get a corporate spec written.  I talked to
them and they said that as a starting point they may use the Cypress spec
as a model.

.H 2 "Technical Questions"

There were a number of technical questions that I had.  I had sent a list
of questions to them about 2 weeks before I went.

.H 3 "Reliability"

I had a number of questions on reliability.  They have a goal of 100 ppm AQL
and they believe that they are meeting this goal but do not have enought data
to verify it.  I asked them what there goal was for field failure rate.  The
person that could answer that question was not in and they said that they would
get back to me with the answer.

Their 4K bit part had no die coat and had no soft errors when exposed to an
alpha particle source.  The 16K bit parts do have a die coating.  They had
no errors when exposed to the alpha particle source.  They are still testing
for long term error rate.  They could not tell me what the error rate was
without the coating.

.H 3 "Signal Quality"

I took a simulation of an address line and the told me that the signal looked
fine.  There could be some noise in the signals as long as they got above 2
volts and stayed there in less than 5 nS.  We can start measuring access time
from 1.5 volts.

.H 3 "Multiple Banks"

There should be no problem with switching banks. (This was expected.)  He
did not know of any problem other than bus and VCC noise with having a buffer
conflict but would recommend that we not have a buffer conflict.

.H 3 "Data Setup Time"

We should be careful not to violate the data setup time .  They typically
need 7 nS.  Also static writes will not work.

.H 2 "Future Parts"

They have no plans for doing a 25 nS 2K x 8 part.  They will be capable of
doing this part next year but they do not expect to see a big demand for it.

They plan on having samples of a 16K by 4 25 nS part by the first part of
next year.  They plan on putting it in a 22 pin 300 mil package.  They will
send us a proposed pinout and are willing to consider changing it if we
have problems with it (other sources).  They do not know of a standard.

