.OP
.PF "''Company Confidential       May 8, 1985''"
.DF
5/8/85
Rob Horning
.DE

This is a summary of what I will try to accomplish when I visit Japan
next week.  The four areas that I will try to learn about are CMOS (TTL
compatible) static RAM's,  1 Mbit dynamic RAM's, fast ECL RAM's and
ECL gate arrays.  This are in prioritized order and I do not expect to
spend very much time on the last two areas.

.H 1 "CMOS Static RAM's"

My highest priority objective for the Japan trip is to establish were the 
major static RAM vendors are and were they will be around the first part
of next year in the area of 25 nS SRAM's.  I currently have a lot of data
but I need to expand on it and verify it.  I am sure that there will still
be a lot of unknowns when I return, but I hope to be at a point where
we can feel confident in our cache organization and expansion strategy.

.H 2 "4K x 4 Part"

My main emphasize will continue to be on the 4K x 4, 25 nS part.  I hope to
find how the various spec are different.  I will encourage them to
be compatible with the Cypress specs.

.H 3 "Package"

There is already a standard 20 pin DIP package and pinout.  It is important
that they have this package but this should not be an issue.

I will also ask them about there surface mount plans.  I will encourage them
to try to converge on a standard and let them know that we would prefer
that the standard be a PLCC or other plastic J leaded package.

I will ask them about modules and hybrids.  I am only interested in getting
information in this area and will not try to influence there strategy.  We
do not understand our needs well enough to give them good inputs.

.H 3 "Multiple Banks"

I will ask them about the spec that states that the turn off time is faster
than the turn on time.  If when I leave, we still feel that we may want two
banks, I will strongly encourage then to provide this spec.

I will also ask them about the effects of bus contention.  I will approach
this question from both the two bank situation and the problems with write
cycles.

.H 3 "Schedule"

I will try to get a better feel for schedules.  For most parts all I have is
the estimate for when we can get samples and when the part will be in
production.  I will try to get estimates of the following check points:

.DL
.LI
Preliminary spec.
.LI
Samples
.LI
Final spec.
.LI
Qual samples
.LI
Production parts
.LE

.H 3 "Signal Characteristics and Requirements"

I will try to get as much information as possible on output characteristics.
I will find out how the timing is specified and how it is tested.

I will also ask about input requirements.  I will ask about the effects of
rise time, ringing and other noise.

.H 3 "Other Information"

I will also ask about the following areas.

.DL
.LI
Power (Active and Standby)
.LI
Cost estimates for the next couple of years.
.LI
Failure Rate (Incoming and Field)
.LI
Failure modes
.LE

.H 2 "Other Static RAM,s"

There are several other static RAM's that I will be asking about.  I will
treat these as a lower priority than the 4K x 4, but will try to get the
same information that I listed for the 4K x 4.  The RAM's listed below are in
prioritized order:

.AL
.LI
16K x 4 - This part is important because there is a good chance that it will
be available as a production part when we go into production.  If we decide
that this is not a high risk part,  our cache organization issue would be
solved.
.LI
16K x 1 - If the 16K x 4 part is not available this part may be the best to
use to insure that Cheetah can have a 128K byte cache.
.LI
2K x 8 - Firefox will use this part.  It is already known to be a very low
risk part at 35 nS (Cypress and Toshiba have parts now).  It is a want to 
get a 25 nS part.  I am assuming that Firefox meets it's performance MUST
with a 20 MHz clock.
.LE

I will also be asking about any other parts that may be coming in the future.


.H 1 "1 Mbit Dynamic RAM's"

This is probably the most important part for the other people from HP who
are going to Japan.  MTC plans to start the qual for this part in the first half
of next year.  With our schedule slips it may be a good idea to change the MC
to support these parts.  I will try to get enough technical information
on the 1 Mbit parts to determine what changes would be required.

.H 1 "ECL RAM's and Gate Arrays"

I will ask the marketing people to get me information on fast ECL RAM's
(10 Ns and faster) and ECL gate arrays.  I do not plan on setting up any
meetings with designers.

