
.DF
  From: Rob Horning                              Date: 6/28/85

    To: Jim Couts 41                          Subject: 25 ns SRAM

    cc: Ron Guffin 44UF
        Ed Holland 44UF
        Bill Jaffe
        Marlen Jones 44UF
        Richard Lawrence
        Rick Luebs
        Sang Park 41
        Tarang Patil
        Craig Robinson
.DE

Attached is a timing spec for 25 ns SRAM's.  We would like a corporate
spec written as soon as possible.  We would like to get the specs to the
vendors so that they have time to make changes if they have to or they
can let us know what specs they can not meet.  We tried to assume
conservative specs to prevent the possibility of having to redesign.

We have the same requirements for the 4K x 4, the 16K x 1, and the 16K x 4
parts.  The spec for each parameter is the slower of the Cypress 16K x 1
or 4K x 4.  In addition we would like the following specifications

.AL
.LI
Chip Enable high data hold time - 3 ns
.LI
Write Recovery time - 0 ns
.LI
When Chip Enable goes high the data is left floating on the bus.
.LI
Outputs will provide undershoot clamping.  At -2 Volts they will
provide 5 mA of clamping for 10 nS.  This is a characteristic that most memory
designs take advantage of but has not been specified in the past.
This parameter does not have to be 100% tested.
.LE

If you think that any of the vendors would have problems meeting any of
these specs please let me know as soon as possible.  We are designing
assuming that these specs can be met for all three parts.

Let me know if there is anything that I can do to help get the specs
written.

Thanks.

