.PH "''''''"
.DF
  From: Rob Horning                          Date: 7/12/85

    To: Mark Forsyth                      Subject: CCU/TCU Timing
        Ron Guffin
        Ed Holland
        Bill Jaffe
        Leith Johnson
        Marlin Jones
        Rick Luebs
        David Means
        Tarang Patil
        Craig Robinson
        Darius Tanksalvala

    cc: Jim Couts
        Sang Park
        Richard Lawrence

.DE

This is a proposal for measuring timing on signals going into SRAM's.
If you see any problems
with the method please let me know so that we can correct them.  Everyone
doing simulations and timing measurements involving the CCU or TCU outputs
driving static RAM's should
use this method to measure timing.  I will work on getting this method
in the corporate spec.

.H 1 "Minimum Delay"

A straight line is draw from .4 volts to 2.4 volts that is on the left side
of the signal and just touches it.  The slope of the
line is chosen to maximize the delay at 1.5 volts but must have a transition
time no greater than 4 ns.  This is the same slope as the Cypress spec
that goes from .3 volts to 2.7 volts in 5 ns.  The minimum delay is the 
time that the line crossses 1.5 volts.

.H 1 "Maximum Delay"

The maximum delay is measured in the same way as the minimum delay except
that the line is drawn to the right of the signal and the delay at 1.5 volts
is minimized.

Examples are attached.

