
Howell,

This is summary of the numbers that you asked for.  The budget that I am
most concerned with is the CCU read budget.  This broken down below:

          Address delay -  6.0 ns
          RAM access    - 25.0 ns
          Data delay    -  1.3 ns
          Parity decode -  7.0 ns
                          _______
          Total           39.3 ns

This leaves .7 ns margin at 25 MHz.

Looking at signals it looks like we could cut about .8 ns out of the data delay
and .7 ns out of the Address delay.  This would make the total 37.8 ns or
26.45 MHz with zero margin.

The .7 ns was arrived at by using the same CCU in a random Cheetah and Firefox
and measuring how much faster firefox was.  This was done because we did more
simulations on the Cheetah board than the Firefox board.

