
This is a list of issues concerning the cache and TLB designs that need to
be resolved by the SPU groups (Cheetah and Firefox).  Many of the areas
have overlap and the primary responsibility should reside in just one
of the groups.

.H 1 "RAM Chips"

.AL
.LI
Characterize the RAM chips.  Decide how to model them for both inputs and
outputs.
.LI
Decide what speed and organization to use.
.LI
Decide what vendors to work with.
.LI
Establish qualification criteria and make sure that the testing gets
done.
.LI
Understand failure rates and error rates ant failure mechanisms.
.LE

.H 1 "Array Design"

.AL
.LI
Design the layout.
.LI
Characterize the array and develop SPICE models to be used with the CCU and
TCU SPICE models.
.LI
Optimize the array design to get maximum timing margin.
.LI

.H 1 "Timing Budget"

Work with the chip designers to come up with a timing budget for each
component in the system.

.H 1 "CCU, TCU Definition"

.AL
.LI
Give inputs on pinout to help optimize layout.
.LI
Help with error detection/correction definition.
.LI
Make sure that the RAM chips are testable by software, board testers, and by
the prism tester.
.LE

.H 1 "Expandability"

Decide what static RAM chips coming out in the future should be supported.
How deep of RAM should be supported and how fast.

.H 1 "Performance"

Establish performance requirements and wants and model the performance.

.H 1 "Power"

Estimate power requirements and establish power budgets.

.H 1 "Cost"

Estimate the cost and evaluate trade offs to meet cost goals.

