From root Tue Mar 26 02:53:59 1985
>From jrs Mon Mar 25 15:54:50 1985 remote from hpstob
To:  hpcup4!hpcup3!db hpfcla!meh hpfcla!meier hpfcla!russ-s hpfclr!craig hpfclr!leith hpfclr!rob hpfclr!tom hplabs!means 
To: hpcup4!hpcup3!db hpfcla!meh hpfcla!meier hpfcla!russ-s hpfclr!craig
    hpfclr!leith hpfclr!rob hpfclr!tom hplabs!means
Status: R


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   INFORMATION HARDWARE OPERATION, 3404 Harmony Road
   Fort Collins, Colorado 80525 (303) 226-3800
   _________________________________________________________________________

   FROM: John Spencer                                   DATE: March 25, 1985

   TO: Distribution

   The Following is an addition to the notes from the flipcharts, included
   here is the evaluation we made on the four alternatives.
   _________________________________________________________________________

   PARAMETER       2Kb/1Way        CTU/CDU         CTU/Comm.       CCU/Comm.

   Cost

   Performance     FF +            CH +            FF ++/CH ++     FF ++

   Schedule        -               CH -            VLSI +          VLSI ++

   Risk            -               CH -            VLSI +          VLSI ++ ?

   Resources                       VLSI -/SPU -    VLSI ++         VLSI ++

   MP              VLSI ++         VLSI -          VLSI -          VLSI -

   Impact on PC    FF =            SPU =           SPU -           FF -

   Error Handling                                  SPU -           SPU -

   Rel/Avail.                                      SPU -           SPU -

   External Risk                                   SPU -           SPU -

   Confirmed Kill  UNK             UNK             UNK             UNK

   Manuf. impact   -               -

   Board Testing                                   -               -

   Other Chip impact VLSI +        VLSI -          VLSI -          VLSI -

   FID Var.        +               ++              -               --

   Time for conf.  4 mo.(VLSI cir) 4mo.(VLSI cir)  4mo.(VLSI cir)  SPU 1 mo.
   kill            0 (VLSI comp)   0 (VLSI comp)   SPU 1 mo.       1 mo. VLSI

   Chip Test       +               +               ++              +++

   Diagnosability  +               +

   Growth Path     +                               ++              +++









   I was out of the room with recruiting duties when this process was being
   done.  I notice in the typing of these notes that I have some problems
   with the perception expressed herein.  I want to state my exceptions.

   We must start again with 75% of the circuits of the CSU and TLB if the
   circuit risk is to be reduced to an acceptable level.  These circuits
   are straightforward for the most part but must be designed with great
   care if the problems of the past are not to be repeated.  If any of the
   VLSI chips contain either a 4 transistor dynamic cell or a 6 transistor
   static cell the I/O section must be redesigned.  It is my belief that
   we may be able to show preliminary schematics with simulations within
   a period of a few weeks for most of these circuits, but, to really know
   the are killer solutions the time period is uncertain.  I gave the
   estimate in Friday's meeting of 4 months to know if we have a VLSI
   killer solution.  This time may be shorter but not significantly due to
   to nature of the problem.  The bottom line is that if any fast RAM
   circuits are needed to replace the ones we were designing there is both
   circuit risk and schedule risk.  The CCU and commercial RAMs may not
   have these risk, however, the TLB must follow the same course or we might
   as well do the custom RAM designs for TAG as well.

   These opinions are my own and do not necessarily reflect the views of
   management entirely.












































