.H 1 "Firefox System board ERS"

This is a description of how the Firefox system board works from
a software point of view.  For details on how the system board hardware works
see the system board theory of operation.

.H 1 "Address Space"

The PDH address space is decoded by the Firefox SIU.  All accesses to the PDH
are one byte at a time.  Data is returned on bits 24 - 31.  The other 24 bits
are undefined.  The SIU will do word transactions to the PDC ROM.  The
PDH sees a word transaction as 4 separate transactions.

The PDC is normally accessed in the 1F00_0000 to 1F03_FFFF address space.  It
is also mapped in to the F000_0000 to F003_FFFF address space but not all
bytes can be accessed.  The other PDH hardware is normally accessed in the
F004_0000 to F007_FFFF address space.  It is also mapped to the F003_0000 to
F007_FFFF address space but writes are not allowed there.

.H 2 "PDC ROM"

  1F00_0000 to 1F03_FFFF

There is a jumper on the board to determine if the ROM size is 64K bytes
or 128K bytes.  The board will support 2 128K byte ROM's or 3 64K byte
ROM's.  The last 64K bytes of PDC ROM address space is undefined when
64K byte ROM's are used.
The ROM's are also mapped from F000_0000 to
F003_FFFF, but can only be accessed one byte at a time in this area and
only every fourth byte can be accessed.
If the ROM emulator board is used, it can be written to only in this higher
address space.  Only every fourth byte can be written.

.H 2 "Stable Store"

  F004_0000 to F005_FFFF

The stable store is 2K bytes.  Only one byte can be accessed with every
4 bytes of address space.  The stable store address space is 32K bytes.
It is aliased through the address space.  After writing to stable store
it cannot be accessed for 20 msec.  There is a bit in the status register
indicating when it cannot be accessed.

.H 2 "RTC/Status"

  F006_0000 to F006_FFFF

Like the stable store only every fourth byte can be accessed.  The RTC is
accessed only 4 bits at a time.  These are bits 4 to 7.  Bits 0 to 3 are
status bits with the following definitions.
All reads from this address space will return this information.  Writes will
have no effect on the status bits.

.DL
.LI
bit 0 - Stable store busy  - If this bit is a one, the stable store is doing
a write.  The EEPROM takes as long as 20 msec to complete a write and cannot
be accessed until the write is completed.
.LI
bit 1 - POW_FAIL  - This is the compliment of the MID_BUS POW_FAIL_L signal.
.LI
bit 2 - CNT_ENABLE - This signal goes to the key switch and is used to enable
remote diagnostics.
.LI
bit 3 - SEC_FAIL  - This is the compliment of the MID_BUS SEC_FAIL_L signal.
.LE

.H 3 "RTC"

The 16 nibbles of the RTC chip (MM58274) are aliased through the address space.
The 16 nibbles are briefly described below.  For more information see the
MM58274 data sheet.

.DL
.LI
F006_0000 - Control register - This register contains the data change flag and
the stop/start bit which are used in reading and writing the clock.
.LI
F006_0004 - Tenths of seconds (Read only)
.LI
F006_0008 - Units seconds
.LI
F006_000C - Tens seconds
Tens
.LI
F000_0010 - Units minutes
.LI
F000_0014 - Tens minutes
.LI
F000_0018 - Units hours
.LI
F000_001C - Tens hours
.LI
F000_0020 - Units days
.LI
F000_0024 - Tens days
.LI
F000_0028 - Units months
.LI
F000_002C - Tens months
.LI
F000_0030 - Units years
.LI
F000_0034 - Tens years
.LI
F000_0038 - Day of week
.LI
F000_003c - Clock setting - Used for setting leap year and 12 or 24 hour mode.
.LE

.H 2 "LED Latch and FPCLOCK/DATA"

  F007_0000 to F007_FFFF

This register is aliased through all the addresses in this space.  Bits 0
through 4 are the five LEDS.  These are turned on by writing a zero to the bit.
Bit 5 is the PROCFAULT LED.  Bit 6 is FPDATA and bit 7 is FPCLOCK.

.H 3 "FPCLOCK and FPDATA"

There are two ways of using the FPCLOCK and FPDATA lines.  The first is to
meet the spec of the AP card.  The second is a slower to allow it to be used
in environmental testing.  Using the FPCLOCK/DATA lines will cause the LED's
to be written.  The software must know what is on the LED's so that the same
data can be written out.  The LED register cannot be read.

.H 4 "AP Card Use"

The following procedure should be used to write to the AP card:
.AL
.LI
Write the first data bit to FPDATA.
.LI
Enable the FPCLOCK by writing a one to the FPCLOCK bit.  This will enable the
FPCLOCK and also cause the first data bit to be clocked into the AP card.
.LI
Write the remaining data bits.  All writes to the LED and FPCLOCK/DATA register
will cause a bit to be clocked into the AP card.
.LI
When all the bits have been write disable the FPCLOCK by writing a zero to
FPCLOCK.
.LE

.H 4 "Environmental Test Use"

It was desired to monitor the FPCLOCK and FPDATA lines with a controller during
environmental test.  This required that the FPCLOCK line change slow enough so
that software could detect when it was pulsing.  The following procedure should
be used when the lines are used in this way:

.AL
.LI
Write the first data bit to FPDATA.
.LI
Enable FPCLOCK by writing a one to the FPCLOCK bit.
.LI
Wait long enough to insure the monotor program can see that the FPCLOCK line
has changed.
.LI
Disable the FPCLOCK by writing a zero to the FPCLOCK bit.
.LI
Wait long enough to insure the monotor program can see that the FPCLOCK line
has changed.
.LI
Repeat the above steps until all the bits have been sent.
.LE

.H 1 "Clock Calibration"

The clocks will be calibrated to within .1 ppm (An error
of 1 ppm would cause the clock to gain or loose 2.5 seconds/month.) at the
factor.  The clocks are calibrated by use of software and the EEPROM
on the system board.  This section explains how the calibration constants are
kept in the EEPROM and gives an example of how the software can use these
to insure accurate time.  It will be possible to adjust the
calibration constants with software (in the field) but this should not be
necessary.

The system clock is used to keep time while the machine is powered up and the
TOD clock keeps time when the machine is powered down.  The TOD clock is read at
power up and set to match the system clock when the machine is powered down.


.H 2 "System Clock"

The CR16 interval timer will count at about 12.5 MHz (assuming that Firefox
has a 25 MHz clock).  PDC_TOD will return
a double-precision floating point value equal to the interval timer
frequency in mega-cycles/second.  This value will be used to calculate
a constant that will be added to the CR16 comparison register each time
there is a timer interrupt.  The constant is calculated by dividing
the interval timer frequency by the desired interrupt frequency (in MHz).

The last value written to CR16 needs to be saved in memory (as opposed to
just reading CR16 to get the value) to insure
that the uncertainty in the interrupt response time does not cause the clock
to drift.  The fractional part of the result of adding the count constant
to CR16 should also be saved to be added into the next value.  This will reduce
the drift due to rounding errors.

.DL
.LI
Example:  If count frequency was 15.005 MHz and the interrupt frequency
was 10 KHz the count constant would be 1500.5.  If the fractional part was
not saved the drift would be .5/1500 (333 ppm) which would be 14 minutes per
month.
.LE

.H 3 "Keeping Accurate Time"

This section discusses an algorithm for keeping accurate time with the CR16
interval timer.  There are three procedures involved.  Some constants have
to be initialized, an interval timer comparison register has to be initialized
and the interval timer comparison register has to be updated.

There are four 32 bit words of memory that need to be initialize and updated:
.DS
	count - This is the number of interval timer counts between
                interrupts.
	count_fraction -  This represents the fraction number of counts
		to make it come out exact.
	count_save - This is used to save the last value loaded into
		CR16.
	fraction_save - This is the remainder from the last time the
                value to load into CR16 was calculated.
.DE

It is assumed that the following two double-precision floating point numbers
will be passed to the routine that initializes the constants:

.DS
	clock_freq - The frequency at which CR16 is counted.
	interrupt_freq - The frequency at which CR16 is to interrupt.
.DE

The following algorithm initializes count and count_fraction.  This is only
executed at power up.

.DS
	begin
{Making the most significant bit of temp1 and temp2 0 simplifies 
the algorithm}
	temp1:=(the 31 most significant bits of the fraction part of
		clock_freq)/2
	temp2:=(the 31 most significant bits of the fraction part of
		interrupt_freq)/2
	temp3:= 2 exp (mantissa of clock_freq - mantissa of
                interrupt_freq)
.DE
.DS
{calculate count by dividing the clock frequency by the interrupt rate}
	count := 0
	while temp3 > 0 do
		begin
		if temp2 < temp1  do
			begin
			count := count+temp3
			temp1 := temp1-temp2
			end
		temp3 := temp3/2
		temp1 := temp1*2
		end
.DE
.DS
{calculate the fractional part by dividing the remainder}
	count_fraction:=0
	temp3 := 2 exp 31
	while temp3 > 0 do
		begin
		if temp2 < temp1  do
			begin
			count_faction:= count_faction+temp3
			temp1 := temp1-temp2
			end
		temp1 := temp1*2
		temp3 := temp3/2
		end
	end
.DE

The following initializes the CR16 counter, count_save, and fraction_save.

.DS
	begin
	count_save := CR16+count
	CR16 := count_save
	fraction_save := count_fraction
	end
.DE

The following updates CR16, count_save, and fraction_save.

.DS
	begin
	fraction_save := fraction_save+count_fraction
	if overflow then count_save := count_save+1
	count_save := count_save+count
	CR16 := count_save
	end
.DE

.H 2 "TOD Clock"

The TOD clock is implemented with a National MM58274.  The data sheet should
be consulted for details on how to set and read the time.  The TOD clock
keeps time in years, months, days, hours, minutes, and seconds.  The PDC
must translate this into seconds when it reads the time and back to
the TOD format from seconds when it sets the time.  A calibration
constant will be saved in the EEPROM.  This will allow an inexpensive,
low accuracy crystal to be used with the clock chip without the problems
of a trimmer capacitor and still enable it to keep very accurate time.

.H 3 "Setting The TOD Clock"

The following things are done to set the TOD clock:
.AL
.LI
The time is received by the PDC as seconds since 00:00:00, January 1, 1970.
(The microseconds word is ignored.)
.LI
This number is multiplied by the inverse of the calibration constant.  The
inverse of the calibration constant will be stored along with the calibration
constant so that the PDC does not have to do a divide.
.LI
The seconds are converted to the TOD clock chip format.
.LI
The time is written to the TOD clock chip.
.LE

.H 3 "Reading the TOD Clock"

The following steps are taken to read the TOD clock:
.AL
.LI
The TOD clock is read.
.LI
The TOD clock chip format is converted to seconds since 00:00:00, January 1,
1970.
.LI
This value is multiplied by the calibration constant.
.LI
The microseconds word is set to zero.
.LE

If it takes a long time to read and write the clock it may be necessary
to add an offset when the clock is read and written to keep the clock
from drifting.

.H 1 "Stable Store Allocation"

This section describes how the stable store is used.  There is information
in stable store that is required to be valid and is changed by the operating
system at times.  The stable store is implemented with an EEPROM.

The stable store takes a long time to write and so provisions have been made
to insure that bad data is not written in the event of a power fail.
The stable store is divided into 4 areas (512 bytes each).  The Firefox
PDC always writes to stable store in double word blocks.

.H 2 "The First Two Areas"

The first two areas are duplicates of each other.  They contain the information
needed by the operating system.  For details on what this information is see
the IO Initialization ACD.  This information in kept in two areas to insure
that a valid copy is available if power goes down while the information is being
changed.  A separate check sum is keep for each area.

.H 2 "The Third Area"

This area is used for PDH information.  At this time the only thing keep in
this area is the calibration constants for the real time clock and the system
clock.

.H 3 "System Clock Frequency"

This is a double-precision floating point number, that gives the exact
frequency of the CR16 counter (about 12.5 MHz).  This number is returned to the operating
system and is intended to be used to keep real time during power up.  It
is located in the first 8 bytes of the PDH area (MSB first)

.H 3 "Real Time Clock Calibration Constant"

The second 8 bytes of the PDH area contain the calibration constants for the
real time clock.  The first 4 bytes contain the constant that the real time
is multiplied by when it is read (MSB first).
If the time is exact, the constant will
be 80000000 Hex.  If it is slow it will be larger, and if it is fast it will
be lower.  When the time is read it is multiplied by the calibration
constant and then multipled by two.  The most significant word of this
operation gives the corrected time.

The next 4 bytes contain the constant that the time is multipled by before
it is written to the real time clock.  This number is the effective inverse of
the first number.  It is provided so that the PDC does not have to do a divide.

.H 3 "Number of Tic's per 10 msec."

Bytes 28 through 31 (hex address) contain the number of tic's of the CR16 counter in 10 msec
(LSB first).
The CR16 counter counts at one half the rate of the system clock (about 12.5
MHz).  This number is not supposed to be used when accuracy is needed but it
will be made exact on Firefox anyway. (UNIX uses it to keep real time.)

.H 2 "The Fourth Area"

This contains the check sums for the other three areas.  It is divided into
three areas on double word boundaries. Each area consist of 168 double word
entries.  The double word is divided into two words.  The first word contains
the check some for the corresponding area.  The second word contains a count.
Every time that a double word is written to stable store the check sum is
recalculated and written and the count is incremented.  The EEPROM can only
be written to 10000 times and so the count is needed to insure the the check
sum is not written to more than 10000 times.  When the count reaches 9500 the
next check sum location is used.  The check sum area is treated special because
each time any double word location is written, the check sum is updated and
so this area will be written much more often than other areas.

