11/12/85

This is a summary of the MID_BUS timing for the Firefox CA chip.

The clock traces will have to be measured and meet the specifications
mentioned below.

.DF

NCD

Item                     min       max

Trace 3.5 inches          0.6       0.7
Delay line               20.2      25.0
Trace 1 inch              0.1       0.2
AS1032                    1.0       5.5
Drive from 4.5 Volts      0.0       1.0
Trace 1.5 inches          0.2       0.3
                         _____     _____
                         22.1      32.7
.DE
.DF

NCR

Item                     min       max

Trace 3.5 inches          0.6       0.7
AS1032                    1.0       5.5
Drive from 4.5 Volts      0.0       1.0
Trace 1.5 inches          0.2       0.3
                         _____     _____
                          1.8       7.5
.DE
.DF

Board delay (data path)

Item                      min       max

NCD                       22.1      32.7
NMOS                       2.9       9.0
Trace 1 to 4 inches        0.1       0.8
AS245                      2.0       7.5
                          _____     _____
                          27.1      50.0

Spec                      19.0      50.0
.DE

.DF
Board Delay (enable path)

Item                      min       max

NCR                       1.8        7.5
NMOS                      3.9       15.55
Trace 1 to 4 inches       0.1        0.8
AS243/245                 2.0        9.0
                          ____       ____
                          7.8       32.85

spec                      0.0       50.0
.DE

.DF
NMOS/TTL buffer conflict

Tracking is assumed.  Part is due to the fact that NCD and NCR share common
pathes and part is due to the buffers being in the same package and both are
driving simulare loads.

Item

NCD min             22.1 
NCR max           -  7.5
NMOS skew         -  6.0
AS243/245         -  9.5
Tracking      1.0
                   _____
                     0.1

spec                 0.0
.DE

.DF
Buffer disable

I do not have a spec for the NMOS delay but it will be much less than 65.
It is clocked off the 50 ns edge.

Item

NCR max             7.5
AS243/245          11.0
Trace 4 inches      0.8
NMOS               65.0
                   ____
                   84.3

spec               85.0
.DE
.DF


Below is the timing calculations for the PDH MID_BUS timing.

clock

Item               min      max

Trace               0.5      0.75
Delay line         20.3     25.1
Trace               0.35     0.7
AS02                1.0      4.5
                   _____    _____
                   22.15    31.05
.DE
.DF

SLAVE and WAIT low

Item

Clock              22.15    31.05
AS74                4.5      9.0
AS244               2.5      7.5
                   _____    _____
                   29.15    47.55

spec                0.0     50.0
.DE
.DF

WAIT high

Item

Clock               22.15    31.05
AS74                 3.5      5.0
AS244                2.0      6.2
                    _____    _____
                    27.65    42.25

spec                19.0     50.0
.DE
