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These are issues that still need to be resolved on the PDH portion
of the CPU board.

The following issues are high level issues that effect the design.

.DL
.LI
How accurate does the CPU clock have to be?  How accurate does the TOD clock
have to be?  Can these accuracies reliably implemented at a reasonable cost?
.LI
How secure does the serial number have to be?  Is it going to be used to
provide software security?
.LI
What are the implications of having an inverted bit on the PDC ROM?  Can
this be easily changed?  Is it ok to have production proto's with the bit
inverted and the next rev PC board with the bit not inverted?
.LI
Is it worth while to make the PDC ROM and NVM faster?  How hard is this to do?
.LI
Make sure that it is ok to take control of MID_BUS without doing a cycle
and to drive the address and data without driving parity.
.LE

Following are design problems that need to be solved.

.DL
.LI
Find and fix the problem with the PAL.
.LI
Make cycles abort when the MID_BUS error signal is asserted.
.LI
Make the MID_BUS timing work with margin.
.LE

The following are things that need to be evaluate and maybe redesigned.

.DL
.LI
The TOD clock chip and EEPROM protection and isolation circuits.
.LI
Evaluate the TOD crystal.  Select the crystal and design a method for
calibrating the clock.
.LI
Evaluate the battery alternatives.
.LE

