.DF
From: Rob Horning                             Date: April 23, 1984

  To: Mark Biegert                         Subject: Firefox RAM
      Leith Johnson                                 design review
      Tom Meyer
      Fred Richart
      Craig Robinson
      Tom Spencer
      Jack Burkman
      Paul Febvre
      Mike King
      Fred Mann
      Larry Maple
      Mike Myshatyn
      Dan Shaner
      Brian Sharpe
      Andy Vogen
      Mark Ludwig
      John Wheeler
      Wayne Covington
      Dave Deane
      Rick Greer
      Ashton Delahoussaye
      Ron Rogers
      Wally Wahlen

  cc: Denny Georg
      Warren Pratt
.DE

A design review for the Firefox memory board will be held on Thursday, April 26
at 1:00 in 1LC10.

I will discuss the general design and design approach.  In most of the areas
that will be discussed I will not go into very deep detail because the details
have not been worked out.

I would prefer to discuss details in smaller groups or individually rather than
using everyone's time discussing details that are not of concern for most people
at the design review.

I have attached a summary of what I plan to discuss and also summaries of some
of the areas I have started to investigate.
.bp


.H 1 "DESIGN REVIEW TOPICS"

This is a summary of what will be covered at the Firefox RAM board design
review.  The purpose of the design review is to bring every one up to
speed on the RAM board and to get feedback on the general design and design
approach.  I would like to limit the time spent on each of the areas listed
below to about 15 or 20 minutes.  I have the room reserved until 4:30 so that
any of the areas can be discussed further if there is a need.

.H 2 "Agenda for April 26"
.DL
.LI
Introduction                        1:00
.LI
General Description                 1:05
.LI
The Controller                      1:25
.LI
RAM Array Testing                   1:45
.LI
RAM Chip Testing                    2:10
.LI
RAM Board Testing                   2:30
.LI
Further Discussion                  2:50
.LE

.H 2 "General Description"

The general features of the board are listed below.
.DL
.LI
Size - Loading options for either 1 Mbyte or 2 Mbyte.  The board is physically
7.175" by 6.75".
.LI
RAM Chips - Uses 120 ns 256K by 1 DRAM's with the nibble mode feature.
.LI
ECC - There are 7 correct bits to provide single bit soft error correction
and can also correct double bit errors where one of the errors is caused
by a known hard failure.
.LI
Interface - Designed for a 10 MHz MID_BUS.
.LI
Power - Requires about 13 watts stand-by and 22 watts active.
.LI
Control - The interface to the MID_BUS and the control of the RAM array will
be provided by a Firefox custom NMOS III chip being designed by STO.
.LI
Layout - The RAM array will use the surface mountable PCC package for the
RAM chips and any TTL buffers required.  The discrete components will also
be surface mountable.
.LE

.H 3 "Contingencies"

There are two major areas that are considered critical for getting the RAM
board done on schedule.  These are getting the surface mount process in
place (mainly getting RAM chips)
and having the RAM controller when it is needed.  At this time it is being
assumed that everything will be in place and the contingencies will not
have to be taken.

.H 4 "Surface Mount"

If the surface mount process can not be put in place or the RAM's are not
available there are two things that could be done.  We could do a 1 Mbyte card
with the same physical size of we could do a larger 4 Mbyte card.  It is
assumed that four Mbytes could fit on a large MID_BUS card.  This assumption
has not been verified.  We will decide in June if we need to pursue one
of these contingencies.

.H 4 "RAM Controller"
It is assumed that the NMOS memory controller will be in place by the time we
need to ship boards.  There could a problem with getting it in time for
production proto.
There are no contingency plans at this time.  Two possibilities
would be to use Indigo memory boards or to do a design that does not need
the NMOS memory controller.

.H 2 "The RAM Controller"

The RAM controller is being designed by STO.  There are two documents that
should be referenced to gain an understanding of the RAM controller:
.DL
.LI
RAM board section of the Firefox ERS
.LI
The Firefox RAM controller Must/Wants list
.LE

These documents are attached.

.H 2 "RAM Array Testing"

.H 3 "Spice Modeling"
Some Spice modeling was done to help determine the best way to lay out the
board and what filtering would be needed.  The test board will help verify
the results of the modeling.  The models will be improved (if more modeling
is needed) by using the actual data from the test board.  A summary of the
testing is attached.

.H 3 "Test Board"
A test board is being laid out to establish and verify the layout and
buffering requirements for the RAM array.  The goals of the layout are:
.AL
.LI
Verify that the design can fit on the board.
.LI
Start to bring PC layout up to speed with the new design requirements for
a surface mount board.
.LI
Experiment with surface mount soldering requirements.
.LI
Characterize the impedance of the lines to establish filtering and buffering
needs.
.LE

.H 2 "Ram Chips"

It would be desirable to have the RAM chip qualification done by MTC
with most of the Firefox requirements coordinated by FSD materials engineering.
At this time it does not appear that we can count on MTC to have the parts
qualified in time to meet our needs.  We are assuming that we will have to
do some qualification testing at FSD.  The plan is to work with TI and Hitachi
(they will be the first vendors able to supply the parts we need) to insure
that we have quality parts for our early production runs.  We will count on
MTC to qualify other vendors.  A preliminary plan for qualifying the RAM
chips is attached.

.H 2 "RAM Board Testing"

The second layout will require a tester to be built to verify that the board
works.  The controller will not be available when this board is done.  It is
a goal to have the PC board debugged when the controller is ready.

I plan to implement the tester so that it interfaces to a S200 GPIO card.
The tester will do block mode reads and writes to the RAM array using the
nibble mode feature.  A more detailed description and a block diagram are
attached.

