.DF
From: Rob Horning                                       Date: 2/14/84

  To: Denny Georg                                    Subject: FIREFOX RAM
                                                              Controller
  cc: Warren Pratt
.DE

Attached is a first pass list of the Musts and Wants for the FIREFOX RAM
controller.  I feel that the schedule will be the most difficult MUST to
meet.  It is important that the controller be staffed as soon as possible
if we are to meet the schedule must.  The odds of success will be greater
if the chip is designed by STO because this will allow better communications
between the people designing the chip and the people designing the board that
will use the chip.

I have been investigating what the controller should do and some implementation
alternatives for meeting the Musts and some of the wants.  I would like to
discuss what I've found with the people designing the chip (when these
people are identified).  Please let me know if there is anything that I
can do to help get the RAM controller design off to a good start.
.bp

This is a list of FSD Musts and Wants for the NMOS III memory controller
being designed for FIREFOX.

MUSTS -

.DL
.LI
Require no faster than 120 nsec. 256K bit RAM chips
.LI
Designed to be used on a 10 MHz MID_BUS and use no other clock.
.LI
No more than 2 MID_BUS wait states added to an 8 word transaction when there is a failed RAM chip.
.LI
Reliably correct double bit errors when one of the errors is caused by a
known bad RAM chip.
.LI
Control one to four 1 Mbyte banks of memory.
.LI
Less than .2% annual failure rate. (8000 hours/year).
.LI
Outputs compatible with TTL buffers (ALS, AS, FAST) and MOS RAMS.  Up
to four loads on each line.
.LI
First working parts 3/85
.LI
production parts 8/85
.LE

WANTS -

.DL
.LI
Work with 150 nsec. 256K bit RAM chips.
.LI
No speed degradation when there is a failed RAM chip.
.LI
Function in a degraded mode when there are two hard failures.
.LI
Control one to eight 1 Mbyte banks of memory.
.LI
Less than .1% annual failure rate.
.LI
Outputs able to drive 78 RAM's with no buffering.
.LI
Minimize the number of wait states.
.LI
Use only a 5 volt power supply.
.LE

