Fred - This is the memory board lab proto section.


.H 3 "Test Board"
A test board is being laid out to establish and verify the layout and
buffering requirements for the RAM array.  The goals of the layout are:
.AL
.LI
Verify that the design can fit on the board.
.LI
Start to bring PC layout up to speed with the new design requirements for
a surface mount board.
.LI
Experiment with surface mount soldering requirements.
.LI
Characterize the impedance of the lines to establish filtering and buffering
needs.
.LE

The board is being laid out as a small MID_BUS card (our best guess at what
the standard will be).  An area is blocked out for where the controller and
MID_BUS buffers go.  This area contains buffers for driving the array.  The
buffers interface the array to a 9836 GPIO card.  The card will not be able
to read data from the memory array but can do read and write cycles.  The
read data will only be observable with an oscilloscope.

.H 3 "Lab Proto Board"

The second layout will require a tester to be built to verify that the board
works.  The controller will not be available when this board is turned on.
It is a goal to have the PC board debugged when the controller is ready.
The layout of the lab proto board will not start until the pin out of the
RAM controller is firm.  It is hoped that only minor changes will be required
for the PC board turn before production proto.

The tester will access the RAM in much the same way as the memory controller
will.  It will do bursts of accesses using the nibble mode feature.  The main
purpose of the tester will be to verify that the PC board is correct and that
the parts are functional.  The tester will be a wire wrapped board that
interfaces to a 9836 GPIO card.

The RAM lab proto board will be tested in Firefox in a limited way.
There will be a small test board designed that will cycle the RAM's
at about the same rate that a bus master would (at the maximum bandwidth).
The board will use the MID_BUS clock but will not respond to MID_BUS
cycles.  RFI testing and class B can be done on the system with the RAM
board present but RAM board failures will not be detected.  The RAM board
can be tested periodicly during the class B testing with the wire wrapped
tester to check to see if any parts have failed.

