.H 1 "SPICE SUMMARY"

This is a summary of the spice modeling that was done and is being done
to help design the Firefox RAM board.

.H 2 "Purpose"

The main purpose of the modeling was to find relative effects of different
bussing and filtering techniques.  The modeling was also used to get an idea
of what the worse case delays might be.

.H 2 "Assumptions"

Most of the testing done assumed the worse case conditions for the slowest
case and the fastest case.

The slow case conditions were:

.DL
.LI
Z = Impedance of the PC trace = 30 Ohms
.LI
TD = Time delay = .8 ns to first RAM, .07 ns between RAM's
.LI
Cr = RAM loading = 10 pF for strobes, 5 pF for addresses
.LI
Rd = Driver output resistor = 30 Ohms
.LI
V = Driver voltage = 4.5 volts high, .4 volts low
.LE

The fast case conditions were:

.DL
.LI
Z = Impedance of the PC trace = 60 Ohms
.LI
TD = Time delay = .3 ns to first RAM, .07 ns between RAM's
.LI
Cr = RAM loading = 3 pF for strobes, 2 pF for addresses
.LI
Rd = Driver output resistor = 20 Ohms
.LI
V = Driver voltage = 4.5 volts high, .1 volts low
.LE

.H 2 "Some of the Results"

.H 3 "Filtering"
Dynamic RAM's have a specification that limits the rise and fall times
to 3 ns.  To insure that this specification is met it is necessary to have a
capacitor in addition to the series damping resistor.  It was found that the
signals could be improved by adding a second resistor between the RAM's and
the capacitor (see drawing and plots).

.H 3 " Bussing"
Bussing the RAM's in a star configuration was compared to bussing them in
line.  It was found that the star configuration could be made faster without
degrading the signals.  The model assumed that the trace to the first
RAM was longer for the star configuration (see drawing and plots).

.H 3 "Address Lines"
Some modeling was done to get an idea of how much delay would be caused by
driving 40 RAM chips.  The modeling showed the delay to be as long as 18 ns.
This will be checked with the test board.  The test board has some lines with
78 RAM address lines connected.

.H 3 "Further Plans for Modeling"

If the test board exposes some problems that have potential solutions that
cannot be easily verified with testing then the models will be improved
(using test board data) and used to compare alternatives.  It s not likely
that this will be done.

Better modeling will also be necessary if the timing specs are pushed to
the limit.  The plan is to have enough timing margin so that this will
not be necessary.  It is preferable to slow down the system instead
of pushing the timing specs.

