This is an explanation of the attached block diagram.

The diagram shows the blocks of the Firefox memory controller that are
involved in correcting double bit errors.

There are two busses.  They are the Data Bus and the Syndrome Bus.

The following things happen when there is a double bit error.  (assuming
that one of the errors is caused by a known hard error that has been
latched into the Syndrome Register.

.AL
.LI
The Data Bus is latched with data from the memory array interface.
.LI
The corrector latch is loaded with data from the Data Bus and the
hamming input is latched.
.LI
The Hamming circuit drives a syndrome on to the Syndrome Bus.
.LI
The corrector drives corrected data on to the Data Bus and
signals the control block that there is a multi-bit error.
(If there was not a multi-bit error the data would be latched by the
MID_BUS interface.)
.LI
The control block signals the syndrome register block
to drive the syndrome register on to the Syndrome Bus.  (If the
syndrome register has not been loaded the ERROR signal on MID_BUS
will be asserted.)
.LI
The corrector dumps corrected data onto the Data Bus.  (This is different than
before because a different syndrome was used to correct the data.)
.LI
The corrector latch is loaded from the Data Bus and the hamming input is
latched.
.LI
The hamming block drives the new syndrome on to the Syndrome Bus.
.LI
The corrector drives the corrected data on to the Data Bus and signals to
the control block that that there is not a multi bit error.
.LI
The MID_BUS latches the data from the Data Bus.
.LE
