.DF

  To: Craig Robinson                                  Date: August 10, 1984

From: Rob Horning                                  Subject: Firefox RAM
                                                            Design
  cc: Mark Ludwig
      Warren Pratt
      John Wheeler
.DE

This is a summary of the two alternatives that are being considered for
solving the Firefox memory timing problems.  Both alternatives have the
the 1 Mbyte RAM board being slower than the two Mbyte board.

.H 1 "Quasi Interleaving"

Everyone has agreed that this is an acceptable alternatives but it may not be
the best.  It is not true interleaving in that only one bank is accessed
at a time.   The data lines of the two banks are still tied together.
Both banks have the row address strobed in at the same time and so after
the four bits are accessed from the first bank, the second bank can be accessed
with only the CAS access time delay.  If only one bank of memory is present
RAS has to be precharged and a second row address has to be strobed in.
This solution uses a 125 ns nibble access time.

.H 2 "Advantages"

The advantages of this solution are listed below.
.AL
.LI
It allows the 168 pin PGA to be used.  (There may however be other reasons
that we go to the 272 pin PGA.)
.LI
The 1 Mbyte performance is better.  (18 states (5.13 MIPS) as opposed to 24
(4.24 MIPS))
.LI
The board layout is the same as the current layout.  There is less chance
of a surprise causing a problem in layout and the layout can begin sooner.
.LE

.H 1 "64 Bit Word"

This alternative does the error correction on a 64 bit word with 8 check
bits.  The nibble cycle time is 200 ns.  Thirty-two bit words can be
supplied to the MID_BUS interface every 100 ns for the 2 Mbyte board and every
200 ns for the 1 Mbyte board.

.H 2 "Advantages"

.AL
.LI
The 2 Mbyte performance is better. (14 states (5.97 MIPS) as opposed to 16
(5.52 MIPS))
.LI
The 2 Mbyte board has about a $50 lower factory cost.
.LI
Timing is easer to meet (200 ns nibble cycle as opposed to 125 ns)
.LI
Control is simpler and thus lower risk of the schedule slipping.  Data and
control signals are always clocked on the same clock phase.
.LI
PC layout is easier because there are 6 fewer RAM's.
.LE

.H 1 "Summary"

The first solution is clearly better for the 1 Mbyte board and the second
solution is better for the the 2 Mbyte board.  The second solution is also
lowest risk for the Firefox product.  The bulk of the sales are expected
to be 2 Mbyte boards and so I feel that we should proceed with the second
solution (64 bit word).  If there are any further concerns we need to get
them settled ASAP so that we can proceed with our designs.

.H 1 "Secondary Issues"

There are a couple of secondary issues that need to be understood.

.H 2 "One Mbyte Implementation of 64 Bit Word"

There are two ways to implement the 1 Mbyte board when there is a 64 bit
word.
.AL
.LI
Supply all 8 check bits and assume that the other 32 bits are all zeros
or ones.  This is the most straight forward way of implementing it but
it requires 40 RAM chips for the 1 Mbyte board.
.LI
Multiplex the two 32 bit words and 4 check bits into one 64 bit word with
8 check bits.  This saves 4 RAM chips but is more complicated.  It may also
be one state slower and will not allow a failed RAM chip to remain in
the system if the whole chip has failed.
.LE

We will most likely go with the first implementation listed.

.H 2 "Slower Writes"

It is likely that writes will be a little slower than reads.  If this is a
major concern we need to know as soon as possible so that we can resolve
the concern.

