
Attached is a schematic for buffer control on the Firefox memory board.

It has a signal (CHIP_CNT2) that turns off  the input buffers on WAIT_L
and SLAVE_L during the tri-state cycle.  The data buffers do not need to be
controlled with two lines because there are wait states and this gives plenty
of time to turn them around.  The table below shows the timing margin:

.DF
.TS
center tab (/) box;
c|c|c|c
l|n|n|l.
 /min/max/Comments
Delay Line/12/21/ (6 gates)
TTL Receiver/4/7/ (2 gates)
NMOS Receiver/1/4/ 
NMOS Driver/1/5/ 
TTL Driver/2/9/ 
 / _____ / _____ / 
Total /20/46/ 
.TE
.DE

The hold time is 20 ns (1 ns margin) and the set up time is 54 ns (4 ns
margin).
