
                                 Fastest      Likely     Slowest

Latch address                     -10          -10         0
Drive address to RAM's             10           10        20
Board Delay                        20           20        20
                                  _____        _____     _____
Row address at RAM's               20           20        40

Skew                                5           10        10
Buffer delay                        0            6         6.5
Board delay                        10           11        13.5
                                 _____         _____     _____
RAS at RAM's                       35           47        70

Hold time                          15           15        15
Skew                                5           10        10
Board delay                        10           20        20
                                 _____        _____     _____
Column address at RAM's            65           92       115

Skew                               10           10        10
Buffer                              0            6         6.5
Board delay                        10           11        13.5
                                 _____        _____      _____
CAS at RAM's                       85          119        145

Access                             60           60         60
Board delay                         3            5          5
                                 _____        _____     _____
Data valid at PUMA                158          184        210

Correct data                       25           30         35
PUMA buffer delay                  10           15         15
Buffer                              7            7          7
Clock delay                         0            7          7
                                 _____        _____      _____
Data valid on MID_BUS             200          243        274

