
.H 1 " Firefox RAM Timing Details"

A timing diagram of the cache line read and write cycles is attached.  The
table below lists the critical timing parameters.

.DF
.TB "Timing Parameters"
.TS
center tab (/) box;
l|l|n|n.
#/Parameter/Min/Max
_
1/Clock to MC outputs/0/15
_
2/Address board delay/0/35
_
3/RAS low board delay/0/45
_
4/CAS low board delay/3/20
_
5/Clock to CAS high/0/15
_
6/CAS high board delay/2/20
_
7/CAS to data valid at MC/0/62
_
8/Data board delay/0/35
.TE
.DE

The timing parameters were arrived at by analyzing the RAM test array board,
doing spice modeling, and by estimating what the MC could do.

The timing specs for the MC must include any skew caused by the clock
circuits.  All the specs given are relative to a perfect
20 MHz dual phase clock.  Read data must be available at the MID_BUS
interface with enough margin to allow for clock delay.  This should not be
difficult but must not be overlooked.

How the critical timing parameters were derived is discussed below.

.H 2 "Clock to MC Outputs"
All of the control, address, and data signals going into the RAM array are
assumed to have no more than 15 ns skew relative to a perfect 20 MHz clock.
The one exception will be discussed later.

.H 2 "Address Board Delay"
This allows for address buffers to be used for a future 4 Mbyte memory board.
There will be about 10 ns worse case margin for a board that is implemented
with double sided surface mount technology.

.H 2 "RAS Low Board Delay"
This is a fairly large time because the MC must drive 39 RAM's and only a
few PC layout restrictions will be put on the RAS signal.  Because of this a
large damping resistor will be needed to insure a glitch free signal.  This
will slow the signal down.  The 45 ns is about 10 ns longer than it needs to
be.  This is because the timing parameters can only be changed in 25 ns
increments.

.H 2 "CAS Low Board Delay"
CAS is the most critical timing parameter.  In order to met the timing
requirements the MC will provide four CAS drivers for each 2 Mbyte
bank of memory.
The PC board will be laid out in a star type configuration were all branches are
balanced and all the RAM's are the same distance from the driver.  This
allows a fairly small damping resistor and thus a faster signal.  The specs
were derived by using spice to model worse case conditions for the fast
and slow cases.  The FET model for the 20 MHz library was used for the
modeling.  It is assumed that this same FET will be used on PUMA.
The timing is only critical on the first access.  There will be an extra
25 ns of margin on the nibble mode accesses.

.H 2 "Clock to CAS High"
This is the one special requirement for the MC timing.  CAS high must track CAS
low to within 13 ns (all other signals are 15 ns).  If the CAS high skew is
15 ns then CAS low must be at least 2 and if CAS low is 0 ns then CAS high
must be no more than 13 ns.  This should be very easy because they are the same
line.  The different CAS's do not have to track each other.  The reason for
this spec is to guarantee CAS precharge on the 1 Mbyte option.

.H 2 "CAS High Board Delay"
This was derived in the same way as CAS low board delay.  This parameter is
only critical on the 1 Mbyte option.

.H 2 "CAS to Data Valid at MC"
This allows 60 ns for the nibble mode access and 2 ns board delay.  The data
lines will be required to be no longer than a total of 6 inches.  The
RAM array test board has some about 12 inches long.  It will take additional
PC area (layers) to shorten the traces.  It is assumed that the input high
voltage for the MC receiver will be 2 volts.  The damping resistor does not
effect this signal because there is very little capacitance on the MC side
of the resistor.  There will be 3 ns setup time at the MC.

.H 2 "Data Board Delay"
This would be easy to meet at about 10 ns.  However, there was an extra 25 ns
in the write cycle and it is used here to allow the tolerance on the damping
resistor to be very wide and then it could be implemented in the MC.

