.H 1 "Firefox Memory Theory Of Operation"

.H 2 "Introduction"

This is the theory of operation for the Firefox memory boards.  Other
documents that would be helpful are the Firefox memory IRS, the 
schematics, the timing diagram, and the MC-F ERS.  The purpose of this document is to explain
the details of the timing and electrical design.

The Firefox memory boards are designed to meet the MID_BUS standard and
the Spectrum IOACD.  At this time there are 2 and 8 Mbyte boards.  The
timing and power allocations were designed to allow a 16 Mbyte board to
be developed by simply adding a second memory array.  The Firefox memory
boards have error correction and allow a single hard failure to be mapped
out without losing the error correction feature (see the IRS for details).

.H 2 "The Memory Array"

The controller is designed to work with either 256K bit or 1M bit RAM chips.
The parts must have the nibble mode feature and require an access time of
120 ns.

The array is arranged as a single bank of 64 bits plus 8 parity bits used for
error correction.


.H 3 " Firefox RAM Array Timing Details"

The table below lists the critical timing budgets for a cache line transfer.

.DF
.TB "Timing Parameters"
.TS
center tab (/) box;
l|l|n|n.
#/Parameter/Min/Max
_
1/Clock to MC outputs/0/15
_
2/Address board delay/0/35
_
3/RAS low board delay/0/45
_
4/CAS low board delay/3/20
_
5/CAS to data valid at MC/0/62
_
6/Data board delay/0/35
.TE
.DE

The timing budgets were arrived at by analyzing the RAM test array board,
doing spice modeling, and by estimating what the MC could do.

All the address and control signals have a 10 Ohm series damping resistor.
The simulations showed that this value was sufficient to prevent ringing.
The value was minimized to get the fastest possible signals.

The timing budgets for the MC include any skew caused by the clock
circuits.  All the specs given are relative to a perfect
20 MHz dual phase clock.  Read data must be available at the MID_BUS
interface with enough margin to allow for clock delay.  This should not be
difficult but must not be overlooked.

How the critical timing parameters were derived is discussed below.

.H 4 "Clock to MC Outputs"
All of the control, address, and data signals going into the RAM array are
assumed to have no more than 15 ns skew relative to a perfect 20 MHz clock.

.H 4 "Address Board Delay"
This allows for address buffers to be used for a future 16 Mbyte memory board.
There will be about 10 ns worse case margin for a board that is implemented
with double sided surface mount technology.  These buffers should not be
required.

.H 4 "RAS Low Board Delay"
This is a fairly large time because the MC must drive 36 RAM's.
The signals are laid out in a star configuration to insure that they are
smooth and glitch free.  The 45 ns is about 10 ns longer than it needs to
be.  This is because the timing parameters can only be changed in 25 ns
increments.

.H 4 "CAS Low Board Delay"
CAS is the most critical timing parameter.  In order to met the timing
requirements the MC will provide four CAS drivers for each 2 (8) Mbyte
bank of memory.
The PC board is laid out in a star type configuration were all branches are
balanced and all the RAM's are the same distance from the driver.  This
allows a fairly small damping resistor and thus a faster signal.  The specs
were derived by using spice to model worse case conditions for the fast
and slow cases.  The FET model for the 20 MHz library was used for the
modeling.
The timing is only critical on the first access.

.H 4 "CAS to Data Valid (RAM Chips to MC-F)"
This allows 60 ns for the nibble mode access and 2 ns board delay.  The data
lines are required to be no longer than a total of 6 inches.  The
RAM array test board has some about 12 inches long.  It will take additional
PC area (layers) to shorten the traces.  It is assumed that the input high
voltage for the MC receiver will be 2 volts.  The damping resistor (built into
MC-F for damping) does not
effect this signal because there is very little capacitance on the MC side
of the resistor.  There will be 3 ns setup time at the MC.

.H 4 "Data Board Delay (MC-F to RAM Chips)"
This would be easy to meet at about 10 ns.  However, there was an extra 25 ns
in the write cycle and it is used here to allow the tolerance on the damping
resistor to be very wide and then it could be implemented in the MC-F.  There
is a damping resistor in each of the data lines of MC-F to prevent ringing.
It is likely that all RAM chips would clamp the ringing, but this would
require a special spec to insure that there would be no problem.

.H 3 "Refresh Timing"

The RAM chips are required to be refreshed in order to retain there data.
The 256K bit chips need the 256 RAS addresses to be refreshed every 4 msec.
The 1M bit RAM chips need the 512 RAS addresses to be refreshed every 8 msec.
The refresh counter and the timing is provided by MC-F.  During normal
operation the MID_BUS clock is used to provide the refresh timing.  During a power
fail there is no MID_BUS clock and so a clock must be provided by the
Memory board.

.H 4 "Power Fail Refresh Clock"

The power fail refresh clock is provided by a Cmos 555 timer.  At the time
the design the data sheet for the part did not have the enough information
to design a clock with reasonable tolerance.  TI agreed that we could add
a line to the HP spec that would give us plus or minus 10% accuracy for
a given set of timing resistors and capacitors.  The table below shows
the period and values used in the spec.

.DF
.TB "555 Timer Spec"
.TS
center tab (/) box;
l|n.
Period    /     6.5 ns
_
R1        /     1690 Ohms
_
R2        /     1690 Ohms
_
C1        /     1500 pF
.TE
.DE

The resistors are 1% and the capacitor is 10%.  This will give a maximum period
of 7.5 micro-seconds.  the memory controller will divide the clock by two to
give a refresh period of 15 micro-seconds.  The RAM chip spec is 15.6
micro-second (8 msec divided by 512).

.H 2 "Power and Voltage Regulation"

.H 3 "Power Budgets"

This is a summary of the power requirements for the Firefox RAM board.  The
power budgets were done assuming a 4 or 16 Mbyte memory board and that address
buffers would be needed.

.H 4 "The RAM Array"

.H 5 "Stand-by Power"

.DL
.LI
Stand-by current - 5mA X 72 chips = 360 mA
.LI
Refresh current - ((65-5) mA X 72 chips)/(12 uS/.23 uS) = 83 mA
.LI
Total stand-by current - 443 mA (886 mA for a 4 Mbyte board)
.LE

.H 5 "Active Power"

.DL
.LI
Chip access - ((75-5) mA X 72 chips)/(1.4 uS/.23 uS) = 828 mA
.LI
Nibble accesses - 3 Accesses X ((60-5) mA X 72 chips)/(1.4 uS/.06 uS) = 509 mA
.LI
Total active power - 443 mA + 828 mA + 509 mA = 1780 mA (2223 mA for a 4 Mbyte
board)
.LE

An active RAM chip will draw (900 mA + 600 mA + (500/2) mA)/39 = 45 mA

.H 4 "NMOS Controller Power"

+5V(S) - 200 mA

+5V - 750 mA

The controller
will draw 30% more power when it is powered up at 0 degrees C.  This
will only be until it warms itself up.

.H 4 "TTL Power"

The TTL power was estimated by dividing the typical power by .8.

74AS243 - 11 parts X 60 mA = 660 mA (Assumes output is a 1 about 100 percent
of the time.)

74AS804 - 2 parts X 12 mA = 24 mA (Assumes output is 1 50% of the time)

Total TTL power (+5V) = 684 mA

For 4 Mbyte board add:

74AS2620 - 5 parts X 82 mA = 410 mA (+5V(S))

.H 4 "Other Power"

The back up clock and regulators take about 10 mA (+5V(S)).

.H 4 "Total Board Power"

.H 5 "2 Mbyte Board"

Stand-by (+5V(S)) - 443 mA + 10 mA + 200 mA = 653 mA = 3.3 watts

Active(+5V(S)) - 1780 mA + 10 mA + 200 mA = 1990 mA = 10 watts

+5V - 750 mA + 684 mA = 1434 mA = 7.2 watts

.H 5 "4 Mbyte Board"

Stand-by (+5V(S)) - 886 mA + 10 mA + 200 mA + 410 mA = 1506 mA = 7.5 watts

Active(+5V(S)) - 2223 mA + 10 mA + 200 mA + 410 mA = 2843 mA = 14.2 watts

+5V - 750 mA + 684 mA = 1434 mA = 7.2 watts

.H 3 "-2V Regulation"

The MC-F requires 2 mA of-2 volts -7.5% +10%.  This is needed during normal
and battery backed operation.  There is not a negative voltage during
battery backed operation and so a charge pump is required.

.H 4 "Charge Pump"

The charge pump uses the 555 timer clock to drive AS808's to provide the
charging current.  The capacitors used are 6.8 micro-farads.  With these
capacitors and the frequency of the 555 timer (130 KHz) there is no droop.

Schottky diodes are used to switch the capacitors because of there low reverse
current during switching.  The lower drop across them is also good but not
needed.

The  worse case load that the drives will see is about 3 mA.  The circuit
will provide a minimum voltage of -3.7 volts ( [Voh-Vol] * 3 + Vdiode *
4).

.H 4 "The Regulator"

The -2V is regulated by an LM324 op amp.  The op amp is used as an inverting
amplifier with a nominal gain of .4.  The 5 volt secondary supply is used
as a reference to get the -2 volts.  The resistors are 8.08K and 20K with 1%
tolerance (1.6% over temperature).
Using the op amp specs and assuming the power supply is plus or minus 5%
shows the output to be between -1.85 V and 2.19 V.

.H 3 "+2.85 Regulation"

The MC-F needs 5 mA at 2.85 volts plus or minus 10%.  This voltage is required
only during normal operation (not battery back up).  This voltage is generated
with 1% resistors and a TL431C shunt voltage regulator from the +5V supply.
With everything worse cased the voltage will be between 2.73 and 2.95 volts.
With the 160 series resistor used the voltage should be within spec for
loads up to 10 mA.

.H 2 "The MID_BUS Interface"

The MID_BUS interface was designed to work in a 16 slot MID_BUS at 10 MHz.
There should be a lot of margin in the Firefox 9 slot, 8.3 MHz, MID_BUS.

.H 3 "The Buffers"

The bus buffers used are AS243's.  These were chosen because of there
short circuit current, there power, and there timing.  The short circuit
current and high speed are required to meet the MID_BUS spec.  The
smaller lower power part (as opposed to a 8 bit part) was chosen because
of concern with cooling a surface mount part.

There are a number of control signals that go into the MC-F without being
buffered.  There was concern that the inputs to the NMOS chip would not
clamp undershoot and it is very likely that the memory board would be the
only type of board on the MID_BUS and so there would be no clamping on
the bus.  Because of this Schottky diodes were added to the lines to provide
clamping.

.H 3 "Clock Timing"

All the timing on MID_BUS is relative to the falling edge of the MID_BUS
clock.  The major specs that had to be met by the memory board are the
set up time (50 ns or less) and the hold time (19 ns or more).  These are
when the memory board is driving the bus.  The memory board must hold the
old data for 19 ns after the clock and have the old data valid by 50 ns.
The 19 ns hold time is provided by a delay line and minimum specs of all
the IC's.  The table below shows all the budgets.

.DF
.TB "Timing Parameters"
.TS
center tab (/) box;
l|n|n|l.
Item/Hold/Setup/
_
TTL Receiver/1.0/5.0/ (AS808)
_
MC-F Driver/2.0/10.0/
_
TTL Driver/2.0/7.5/
_
Delay Line Buffer/1.0/5.0/ (AS808)
_
Delay Line/12.0/22.5/ (See note 1)
.TE

Note 1 - The delay line budget is what is left over after everything else.



.DE

There is a another budget that also has to be met.  This is to prevent a buffer
contention between the MID_BUS buffers and the MC-F.   On a read the MID_BUS
buffers are turned around a signal related to the MID_BUS clock.  The MC-F
start driving on delayed clock.  The signal that turns the buffers around
can be delayed relative to clock by 0 to 7 ns.  The drivers can have as much
as 3 ns additional skew.  This means that the signal that turns around the
buffers can have a total effective delay of 10 ns.  The table below shows
the budgets to meet this spec:

.DF
.TB "Buffer Conflict Timing Parameters"
.TS
center tab (/) box;
l|n|l.
Item/Budget/
_
TTL Receiver/1.0/ (AS808 min delay)
_
MC-F skew/-10.0/
_
TTL Driver/-11.0/ (AS243 turn off)
_
Delay Line (min)/20.0/ (See note 1)
.TE

Note 1 - The delay line budget is what is left over after everything else.



.DE
.H 4 "Delay Line"

The delay line is required to have a delay of between 20 and 22.5 ns.  At
the time of the design there were not reliable surface mount delay lines
and so alternatives were investigated.  Lumped LC circuits were tried and
seemed to work ok but, it was hard to guarantee the delay with all the
tolerances on the parts (mostly the drivers and receivers).  The second
alternative was to use a long trace to get the needed delay.  It was found
that this was feasible and so this is what was done.

The dielectric constant of the PC board is specified to be between 4.4 and
4.8 which gives a delay of between 2.13 and 2.23
ns per foot.  the trace was made 115.5 inches long to give a delay of 20.5 to
21.5 ns.  The delay for a trace between to ground planes is 1.017 times the
square root of the dielectric constant.

Two of the potential problems with the long trace are RFI and the signal
coupling into itself.  To avoid this the trace is between two ground planes
and spaced 45 mils apart with a 15 mil ground trace between the loops.
This has been shown to work very well.  The 8M byte board is spaced more than
this.

Two drivers are used to drive the line to prevent overdriving one driver.
They each drive a 10 Ohm series damping resistor.  The resistors also help
reduce any contention current that may occur due to the drives being different
speeds.

The receiver end of the line is clamped to ground and 4 volts with Schottky
diodes.  Both clock line are pulled to +5 with a 1500 Ohm resistor because
they need to get up to 3.5 volts.

.H 2 "Test Features"

.H 3 "MC-F test Features"

The test strategy for the the memory board was to do no automatic self test
with the MC-F, but to allow software to get at everything on the memory board.
It is possible to write any pattern into the memory and the error correction
bits and to read the data or the error correction bits without having
the error corrector change the data.  Most of the registers in the memory
controller are readable.  See the the IRS for details on how to use the
test features.

.H 3 "Electronic Board Test"

The MC-F was designed with the capability of putting all the outputs into
the high impedance state.  This is done with the following procedure:

.AL
.LI
Power the memory board with the following MC-F pins in the given state:
.DL
.LI
PON (B13) low
.LI
NSEL (U18) low
.LI
NSTRB (U19) high
.LI
NDIN (W18) low
.LE
.LI
Pull PON high
.LI
Clock the following three commands into the MC-F:
.DL
.LI
011110110
.LI
001111111
.LI
001111101
.LE
     Use the following procedure to clock in each command:
.DL
.LI
Drive NSEL high, NSTRB high and NDIN low.
.LI
Drive NSEL low.
.LI
Drive first bit of the command (MSB) on NDIN.
.LI
Drive NSTRB low and then high again to clock in bit.
.LI
Repeat the above two steps until all nine bits of the command are clocked in.
.LI
Drive NSEL high, NSTRB high, and NDIN high.
.LI
Drive NSEL low.
.LI
Drive NSRTB low and then high again.
.LI
Drive NSEL high.
.LE
.LI
The MCF should now be tri-stated.
.LE

The PC board was designed to allow all nodes to be probed from the bottom of
the board.  This is not automatic with a surface mount board.  Some signals
have a feed through even though they only connect to the top layer.

.H 3 "The DIP Port"

There are connector holes on the board to allow a connector to be added for
the DIP port.  There are no plans to load this connector in production.
It was put on only for turn on and evaluation purposes.

