.pl 72v
.MT 4 1
.nr Ls 0
.po 0
.DS
.DE
.SP 5
.TS
tab(:);
cw(4.3i) cw(3.7i) cw(5.0i).
.B
Project Manager - Craig Robinson:FIREFOX:date April 84
.SP 1
Engineer - Rob Horning ::Project 7166
.R
.TE
.SP 2
.in .1i
.TS
tab(:);
c c c c
lw(4.2i) lw(.3i) nw(.3i) lw(4.1i).
.B
OBJECTIVES:MD :%:RESULTS, STATUS
.R
.SP 1
T{
Work with STO on getting the memory controller started.  Keep the Must/Wants
list current.
T}:2:100:T{
I have been working a lot with Mark Ludwig.  The musts/wants list has been
added to the PCD.  I have been keeping it up to date.
T}
.SP 1
T{
Work closely with PC layout to insure that I understand the problems with
laying out the RAM array and to make sure that the bussing is done in a way
that I can do the comparison testing that I need to do.
T}:5:100:T{
The board is now being digitized.  I hope to have PC boards by the end of May.
T}
.SP 1
T{
Continue to work with materials engineering to get parts set up and
qualified for the RAM board.  (The RAM chips are the biggest concern.)
T}:5:100:T{
I should have all the parts that i need for the test array by the end of May.
A letter was sent out to several RAM vendors to get information on how we
stand for getting early production parts.
T}
.SP 1
T{
Review the ERS and update the RAM and Graphics sections.
T}:2:100:T{
Both sections were updated for the distributed version.
T}
.SP 1
T{
Prepare for and hold a design review for the RAM board.  The purpose of the
design review will be to bring people up to date on what I am doing and
to try to get some good feed back on the overall strategy.
T}:3:100:T{
The design review was held on 4/26.  No major problems were found.  It was
a good opportunity for me to summerize my ideas and strategy.  It helped
bring the other functional areas up to speed.
T}
.SP 1
T{
Work with material engineering to insure that MTC is aware of our needs
for RAM chips.
T}:1:100:T{
Materials engineering has an understanding of our needs and will be working
with MTC.  It appears that MTC will not be able to meet our early needs.
T}
.SP 1
T{
Continue to work on the RAM test board tester and the RAM prototype tester.
T}:1:100:T{
I wrote up a turn on plan for Fred and revised my strategy to have a test
board that allows the RAM board to be tested in class B and for RFI.
T}
.SP 1
T{
Update the RAM and graphics perts to have 10, 50 and 90 percent estimates.
T}:1:100:T{
This was done early in the month.
T}
.SP 1
T{
T}:::T{
T}
.TE
.in 10.1i
.sp |12v
.TS
tab(:);
cw(2.8i)
l
c
l
c
l
c
l.
.B
DEVIATIONS, ACTION
.R
.sp |15v
T{
T}
.sp |28v
.B
KEY DECISIONS
.R
.sp |30v
T{
T}
.sp |36v
.B
CONCERNS, CRITICAL ELEMENTS
.R
.sp |38v
T{
T}
.sp |49
.B
SUMMARY
.R
.sp |51
T{
T}

