.pl 72v
.MT 4 1
.nr Ls 0
.po 0
.DS
.DE
.SP 5
.TS
tab(:);
cw(4.3i) cw(3.7i) cw(5.0i).
.B
Project Manager - Craig Robinson:FIREFOX:date Dec 84
.SP 1
Engineer - Rob Horning ::Project 7166
.R
.TE
.SP 2
.in .1i
.TS
tab(:);
c c c c
lw(4.2i) lw(.3i) nw(.3i) lw(4.1i).
.B
OBJECTIVES:MD :%:RESULTS, STATUS
.R
.SP 1
T{
Continue to test the lab proto RAM board.  Test all the memory locations,
look at signals, test regulators, and test the delay line.
T}:5:100:T{
I have read and written every location.  I tested the regulators, the 555 timer
and the delay line.  Some minor problems were found and fixed.
T}
.SP 1
T{
Continue to work with vendors.
T}:1:100:T{
I am working on setting up Hitachi a a RAM vendor.  I have continued to work
with TI on RAM chips and other parts.  I still do not have my 74AS243's.
T}
.SP 1
T{
Turn on RAM exerciser and write the test vectors for the environmental
test.
T}:3:100:T{
The exerciser was built and is working.
T}
.SP 1
T{
Start looking at the PC board delay line experiment.
T}:1: - :T{
The PC board came back late and so I did not get time to do this.
T}
.SP 1
T{
Finish NMOSIII training course.
T}:5:100:T{
Having an understanding of the NMOS III design tools will help me work more
effectively with the MC-F designers. 
T}
.SP 1
T{
Vacation Dec. 24 through Jan. 4. (Three of the vacation days are in January.)
T}:7::T{
T}
.SP 1
T{
Update the RAM PERT by 12/10.
T}::100:T{
T}
.SP 1
T{
T}:::T{
T}
.TE
.in 10.1i
.sp |12v
.TS
tab(:);
cw(2.8i)
l
c
l
c
l
c
l.
.B
DEVIATIONS, ACTION
.R
.sp |15v
T{
T}
.sp |28v
.B
KEY DECISIONS
.R
.sp |30v
T{
T}
.sp |36v
.B
CONCERNS, CRITICAL ELEMENTS
.R
.sp |38v
T{
T}
.sp |49
.B
SUMMARY
.R
.sp |51
T{
T}

