.pl 72v
.MT 4 1
.nr Ls 0
.po 0
.DS
.DE
.SP 5
.TS
tab(:);
cw(4.3i) cw(3.7i) cw(5.0i).
.B
Project Manager - Craig Robinson:FIREFOX:date June 84
.SP 1
Engineer - Rob Horning ::Project 7166
.R
.TE
.SP 2
.in .1i
.TS
tab(:);
c c c c
lw(4.2i) lw(.3i) nw(.3i) lw(4.1i).
.B
OBJECTIVES:MD :%:RESULTS, STATUS
.R
.SP 1
T{
Document the deferences between Firefox and Indigo for the software people.
T}:3:100:T{
This was sent to Nancy Schoendorf on June 15.
T}
.SP 1
T{
Help get the RAM board loaded and turn it on.
T}:2:100:T{
The board was loaded and turned on on June 20.  A proto-type pick and place
machine was used to load the board and the STO vapor phase machine was uses
to re-flow the solder.
T}
.SP 1
T{
Evaluate the RAM array and do some more spice modeling if needed.
T}:6:100:T{
I have taken some measurements with my scope and a TDR.  I also had a Keystone
1 GHz scope from Colorado Springs for a couple of days.  The signals are
slower than I had hoped they would be and so I have started to do some
spice modeling to see what has to be done to make the timing work.
T}
.SP 1
T{
Establish timing requirements for the PUMA memory controller.
T}:3:25:T{
There are still some problems to work out.  I feel that this needs to be my
top priority in July.
T}
.SP 1
T{
Continue to help with the definition of the memory controller.
T}:1:100:T{
I have been working on this and I do not think that there will be any major
problems.  There are a few issues that we need to gain more understanding
on so that they can be resolved.
T}
.SP 1
T{
If time permits work on the lab proto testers and establish the memory
needs for the lab proto.
T}:::T{
Time did not permit.
T}
.SP 1
T{
Vacation
T}:6::T{
T}
.SP 1
T{
T}:::T{
T}
.TE
.in 10.1i
.sp |12v
.TS
tab(:);
cw(2.8i)
l
c
l
c
l
c
l.
.B
DEVIATIONS, ACTION
.R
.sp |15v
T{
T}
.sp |28v
.B
KEY DECISIONS
.R
.sp |30v
T{
T}
.sp |36v
.B
CONCERNS, CRITICAL ELEMENTS
.R
.sp |38v
T{
I have not yet established that the RAM timing will work.
T}
.sp |49
.B
SUMMARY
.R
.sp |51
T{
T}

