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Project Manager - Craig Robinson:FIREFOX:date May 84
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Engineer - Rob Horning ::Project 7166
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OBJECTIVES:MD :%:RESULTS, STATUS
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T{
Check RAM array pen plots and film and order boards.
T}:1:100:T{
The boards came about 5/24.
T}
.SP 1
T{
Work with STO on the MC needs.
T}:3:100:T{
I have been working with Mark Ludwig on definition and more detailed timing
requirements.  It is likely that there will be a wait state added to the
memory accesses.
T}
.SP 1
T{
Review the PCD and update my section.
T}:1:100:T{
T}
.SP 1
T{
Continue to work on getting surface mount parts.  Visit TI to make contacts
and get information on PCC RAM chips.
T}:5:100:T{
No new problems have come up.  I still have not found a suitable voltage
regulator.  The trip to TI was very successful.  Their plans did not meet
our needs, but they have committed to changing there plans to meet our
needs.
T}
.SP 1
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Update RAM and graphics lines on the PERT.
T}:1::T{
This was not necessary because they have not changed significantly.
T}
.SP 1
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Write the 9836 program to drive the RAM array test board.
T}:3:100:T{
I have started to use the program.  It seems to be adequate for the testing
that I need to do.
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.SP 1
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Do first pass design of the lab proto RAM board tester.
T}:3:20:T{
This was a lower priority than some other things that came up this month.
I will not need the tester until the end of September.
T}
.SP 1
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Do first pass of design of the lab proto RAM board exerciser.
T}:2:100:T{
The board is simple and uses common parts.
T}
.SP 1
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Investigate alternatives for non-NMOS memory board for early proto's.
T}:3:20:T{
I did not spend much time on this.
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DEVIATIONS, ACTION
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I got the RAM PC board back sooner than I expected and started testing it.
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KEY DECISIONS
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CONCERNS, CRITICAL ELEMENTS
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SUMMARY
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