.pl 72v
.MT 4 1
.nr Ls 0
.po 0
.DS
.DE
.SP 5
.TS
tab(:);
cw(4.3i) cw(3.7i) cw(5.0i).
.B
Project Manager - Craig Robinson:FIREFOX:date November 84
.SP 1
Engineer - Rob Horning ::Project 7166
.R
.TE
.SP 2
.in .1i
.TS
tab(:);
c c c c
lw(4.2i) lw(.3i) nw(.3i) lw(4.1i).
.B
OBJECTIVES:MD :%:RESULTS, STATUS
.R
.SP 1
T{
Help get the IO_ACD firmed up.  Write an IRS for the Firefox memory
board.
T}:6:100:T{
The IO_ACD and MID_BUS meetings went very smoothly.  All the issues that
effect the memory controller are resolved.
T}
.SP 1
T{
Test the lab proto RAM board.  Look at signals and exercise all the RAM
locations.
T}:8:80:T{
I have another day are two of work to get to the point were I've tested
the whole board and looked at most of the signals.the whole board and looked at most of the signals.
T}
.SP 1
T{
Take the RAM board exerciser and the delay line tests through PC layout.
T}:2:100:T{
The Board is being fabricated.
T}
.SP 1
T{
Work with the surface mount vendors.
T}:2:100:T{
I have continued to work with TI and the other surface mount vendors to help
insure that we will not have problems getting surface mount parts.
T}
.SP 1
T{
If time permits look investigate if the error correction algorithm is
patentable.
T}:2: - :T{
Time did not permit.
T}
.SP 1
T{
T}:::T{
T}
.SP 1
T{
T}:::T{
T}
.SP 1
T{
T}:::T{
T}
.SP 1
T{
T}:::T{
T}
.SP 1
T{
T}:::T{
T}
.SP 1
T{
T}:::T{
T}
.SP 1
T{
T}:::T{
T}
.TE
.in 10.1i
.sp |12v
.TS
tab(:);
cw(2.8i)
l
c
l
c
l
c
l.
.B
DEVIATIONS, ACTION
.R
.sp |15v
T{
I spent a week taking the NMOSIII training course.

Spent a half day making a schedule and investigating non-surface mount
RAM board.
T}
.sp |28v
.B
KEY DECISIONS
.R
.sp |30v
T{
T}
.sp |36v
.B
CONCERNS, CRITICAL ELEMENTS
.R
.sp |38v
T{
T}
.sp |49
.B
SUMMARY
.R
.sp |51
T{
T}

