.pl 72v
.MT 4 1
.nr Ls 0
.po 0
.DS
.DE
.SP 5
.TS
tab(:);
cw(4.3i) cw(3.7i) cw(5.0i).
.B
Project Manager - Craig Robinson:FIREFOX:date September 84
.SP 1
Engineer - Rob Horning ::Project 7166
.R
.TE
.SP 2
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lw(4.2i) lw(.3i) nw(.3i) lw(4.1i).
.B
OBJECTIVES:MD :%:RESULTS, STATUS
.R
.SP 1
T{
Prepare for and make a presentation at the PUMA I to L meeting.
T}:3:100:T{
The meeting went well.  The MC-F went I to L.
T}
.SP 1
T{
Review and document change proposals for the IO_ACD meeting on 9/17.
Also attend the meeting.
T}:3:100:T{
All the changes that we need were accepted.  It should not be a problem
for the Firefox memory board to comply with the IO_ACD.
T}
.SP 1
T{
Work with PC layout and keep the schematic updated as the MC-F pinouts
and requirements change.
T}:4:100:T{
There were several things that changed and required the layout to change.
The most notable were the pinout and the charge pump changes.
T}
.SP 1
T{
Select and order parts for the lab proto.
T}:3:100:T{
All the parts have been ordered.  There are some buffers that may not come
in and so these may have to be hand loaded onto the first board when they
come in.  I will hold off building more than one board until all the parts
do come in.  They should arrive some time in October.
T}
.SP 1
T{
Red line the RAM board.
T}:2:100:T{
The board was finished and the package sent out about 10/3.
T}
.SP 1
T{
Work with TI to make sure that everything is going as planned with the RAM
chips.
T}:2:100:T{
We met with TI and settled some small issues that came up.  Everything is
progressing on schedule.  I have received my first 250 parts.
T}
.SP 1
T{
Finish the timing specs (semaphores).
T}:1:100:T{
All the timing has been worked out.
T}
.SP 1
T{
Continue to work on the RAM tester.
T}:1:100:T{
I finished designing the tester and have it entered on EGS200.
T}
.SP 1
T{
T}:::T{
T}
.TE
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cw(2.8i)
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c
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l.
.B
DEVIATIONS, ACTION
.R
.sp |15v
T{
T}
.sp |28v
.B
KEY DECISIONS
.R
.sp |30v
T{
T}
.sp |36v
.B
CONCERNS, CRITICAL ELEMENTS
.R
.sp |38v
T{
T}
.sp |49
.B
SUMMARY
.R
.sp |51
T{
T}

