.pl 72v
.MT 4 1
.nr Ls 0
.po 0
.DS
.DE
.SP 5
.TS
tab(:);
cw(4.3i) cw(3.7i) cw(5.0i).
.B
Project Manager - Craig Robinson:FIREFOX:date August 85
.SP 1
Engineer - Rob Horning ::Project 7910
.R
.TE
.SP 2
.in .1i
.TS
tab(:);
c c c c
lw(4.2i) lw(.3i) nw(.3i) lw(4.1i).
.B
OBJECTIVES:MD :%:RESULTS, STATUS
.R
.SP 1
T{
Continue to work with vendors on SRAM specs.
T}:3:100:T{
I have continued to work with the SRAM vendors on the specs.  We are refining
them to insure that the way that we measure timing is valid.  There have been
no big problems.
T}
.SP 1
T{
Layout the SRAM arrays and measure the worse case traces.  This includes
getting by Gator box system set up.
T}:5:90:T{
I have my Gator box system working (I still have to borrow memory to run EGS).
I have the parts placed and feel confident that I can hook them up.  I have
made conservative estimates of how long the traces will be.
T}
.SP 1
T{
Model (using short models) the SRAM arrays and decide what will be
needed for termination.
T}:4:100:T{
I have decided to use both a series resistor and a termination diode.  The
line is too high Q with out the resistor ( not very predictable) and the
diode lets me keep the resistor value down to a value that allows the signal
to be fast.
T}
.SP 1
T{
Check the details of all the types of accesses to the SRAM arrays.  Make sure
that the 35 ns SRAM's will run at 20 Mhz.
T}:3:75:T{
The timing do not yet work.  I spend a lot of time on this.  I have looked at
most of the types of accesses.  The CCU writes are were most of the problems
are.
T}
.SP 1
T{
Work on memory board issues.  Document change requirements for MC-F.  Do
some first pass estimates of the feasibility of fitting the 1 Mbit RAM chips on
the memory board.
T}:3:100:T{
Only a couple of minor issues came up.  I documented the changes to MC-F and
gave them to Mark Ludwig and Russ Mason.  I worked with Larry Maple to get
the spacing requirements for the chips.  I am fairly sure that they can fit
on the board without putting the caps under the RAM chips.
T}
.SP 1
T{
Evaluate how the new board partitioning effects PDH.
T}:2:100:T{
It looks like the board partitioning will very little effect on the PDH.
T}
.SP 1
T{
Start investigation of NIO chip requirements.
T}:2:100:T{
I have an idea of what will be required to do NIO.  I let them know that
we are concerned about the clock not being the same as MID_BUS.
T}
.SP 1
T{
Prepare for and attend CCU/TCU I to L if it is in August.
T}:1: - :T{
This did not happen.
T}
.SP 1
T{
Vacation 9/6
T}:1::T{
T}
.TE
.in 10.1i
.sp |12v
.TS
tab(:);
cw(2.8i)
l
c
l
c
l
c
l.
.B
DEVIATIONS, ACTION
.R
.sp |15v
T{
T}
.sp |28v
.B
KEY DECISIONS
.R
.sp |30v
T{
T}
.sp |36v
.B
CONCERNS, CRITICAL ELEMENTS
.R
.sp |38v
T{
T}
.sp |49
.B
SUMMARY
.R
.sp |51
T{
T}

