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.nr Ls 0
.po 0
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Project Manager - Craig Robinson:FIREFOX:date March 85
.SP 1
Engineer - Rob Horning ::Project 7910
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OBJECTIVES:MD :%:RESULTS, STATUS
.R
.SP 1
T{
Come up to speed on the parts of the CPU board that I am responsible for.
Evaluate what problems need to be solved and develop a plan for solving
the problems.  If time permits start working on solutions. 
T}:12:100:T{
I have made up a list of things to look into.  There does not appear to be
a problem with meeting the schedule and so I am approaching the problems
by solving the highest level concerns first and working down toward the more
detailed problems.  I have done a first pass ERS for the RTC and worked on
the definition of the NVM.
T}
.SP 1
T{
Work with PC layout.  Help make changes.  Red line the board.  Make sure
that the film and drill tape are in a form that the PC vendor can use.
T}:3:50:T{
The board is taking longer to change than expected.  All the footprints have
changed and I added some diodes to protect the NMOS chip.  I have not been
pushing to get it done because it looks like we can get proto boards in
about a week.
T}
.SP 1
T{
Continue to work with the MC chip designers.
T}:2:100:T{
I have kept in touch and resolved a couple of issues (added protection diodes).
T}
.SP 1
T{
Continue to work with surface mount vendors.
T}:1:100:T{
I have continue to keep in touch with the progress of the vendors.
T}
.SP 1
T{
Distribute the test responsibility list and keep it up to date.
T}:2:-:T{
I have not received feedback on the rough draft yet.
T}
.SP 1
T{
Update the RAM PERT and the state variables.
T}:1:100:T{
T}
.SP 1
T{
T}:::T{
T}
.SP 1
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T}:::T{
T}
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DEVIATIONS, ACTION
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.sp |15v
T{
I spent about 5 days working on the cache/TLB problems and looking into the
availability of fast static RAM's.
T}
.sp |28v
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KEY DECISIONS
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.sp |30v
T{
T}
.sp |36v
.B
CONCERNS, CRITICAL ELEMENTS
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.sp |38v
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.sp |49
.B
SUMMARY
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.sp |51
T{
T}

