.pl 72v
.MT 4 1
.nr Ls 0
.po 0
.DS
.DE
.SP 5
.TS
tab(:);
cw(4.3i) cw(3.7i) cw(5.0i).
.B
Project Manager - Craig Robinson:FIREFOX:date May 85
.SP 1
Engineer - Rob Horning ::Project 7910
.R
.TE
.SP 2
.in .1i
.TS
tab(:);
c c c c
lw(4.2i) lw(.3i) nw(.3i) lw(4.1i).
.B
OBJECTIVES:MD :%:RESULTS, STATUS
.R
.SP 1
T{
Continue to work on CCU/TCU issues that come up.  Continue to help
with definition.
T}:4:100:T{
The major issues have been resolved.  The cache organization still needs to
be finalized.
T}
.SP 1
T{
Prepare for and visit Cypress.
T}:1:100:T{
The Cypress visit went well.  I wrote a report summerizing what I found out.
T}
.SP 1
T{
Prepare for and visit Japanize vendors.  Write a report on my findings.
T}:17:100:T{
I got a good picture of where they are as far as SRAM's and I got the message
across that we need very fast SRAM's.  I will finish the summary of
what I found on SRAM's in May and a summary on 1 Mbit DRAM's shortly
after.
T}
.SP 1
T{
Address any RAM board issues that come up.  Help get the board read to build.
T}:1:100:T{
I got the PC boards back.  There is a problem but I think I will build at least
one anyway.
T}
.SP 1
T{
Update the memory board state variables.
T}::100:T{
T}
.SP 1
T{
T}:::T{
T}
.TE
.in 10.1i
.sp |12v
.TS
tab(:);
cw(2.8i)
l
c
l
c
l
c
l.
.B
DEVIATIONS, ACTION
.R
.sp |15v
T{
T}
.sp |28v
.B
KEY DECISIONS
.R
.sp |30v
T{
T}
.sp |36v
.B
CONCERNS, CRITICAL ELEMENTS
.R
.sp |38v
T{
T}
.sp |49
.B
SUMMARY
.R
.sp |51
T{
T}

