.pl 72v
.MT 4 1
.nr Ls 0
.po 0
.DS
.DE
.SP 5
.TS
tab(:);
cw(4.3i) cw(3.7i) cw(5.0i).
.B
Project Manager - Craig Robinson:FIREFOX:date November 85
.SP 1
Engineer - Rob Horning ::Project 7910
.R
.TE
.SP 2
.in .1i
.TS
tab(:);
c c c c
lw(4.2i) lw(.3i) nw(.3i) lw(4.1i).
.B
OBJECTIVES:MD :%:RESULTS, STATUS
.R
.SP 1
T{
Get the 8 Mbyte board ready for PC layout.  Decide how it should be layed out
and get the layout started.  Address other memory issues that come up.
T}:5: 80:T{
This was made a low priority and so I did not go into layout.  I am going to
have PC layout do the board.  I should be able to get 1 Mbit RAM chips by March.
I am ready to go into PC layout.
T}
.SP 1
T{
Resolve the A priority PDH issues.  Work with Leith on schematic and layout.
Upgrade the PDH in the proto-type.
T}:6:100:T{
I now have primary responsibility for this board.  I resolved all the A
priority issues and some of the B.  I am in PC layout.
T}
.SP 1
T{
Layout the SRAM arrays on the new second rev CPU board.
T}:4:100:T{
The arrays are layed out.  We are still checking them.
T}
.SP 1
T{
Help resolve any CCU/TCU issues that come up.
T}:2:100:T{
We have the definition done.  We have decided on the edge placement for
the SPL.  An issue came up concerning testing the SRAM's but there should
be no problem.
T}
.SP 1
T{
Look into getting fast SRAM's.
T}:2:100:T{
I looked into this a little and pointed out that this was not as easy and
risk free as it first appears.  The issue was dropped.
T}
.SP 1
T{
investigate what needs to be done to turn on and test memory boards.
T}:2: - :T{
I did not spent much time on this.
T}
.SP 1
T{
T}:::T{
T}
.SP 1
T{
T}:::T{
T}
.TE
.in 10.1i
.sp |12v
.TS
tab(:);
cw(2.8i)
l
c
l
c
l
c
l.
.B
DEVIATIONS, ACTION
.R
.sp |15v
T{
T}
.sp |28v
.B
KEY DECISIONS
.R
.sp |30v
T{
T}
.sp |36v
.B
CONCERNS, CRITICAL ELEMENTS
.R
.sp |38v
T{
T}
.sp |49
.B
SUMMARY
.R
.sp |51
T{
T}

