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Project Manager - Craig Robinson:FIREFOX:date October 85
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Engineer - Rob Horning ::Project 7910
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OBJECTIVES:MD :%:RESULTS, STATUS
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Help with the turn on and check out of the CPU board and the PDH.
T}:5:100:T{
This did not take very much time because there were no problems wit the PDH.
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Re-do the SRAM array simulations with the corrected FET and PGA models.
T}:3:100:T{
I did the new simulations and there were some small problems but these have
been solved.  There is plenty of margin on Firefox.
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Address CCU/TCU issues and check all the timing for the non critical
accesses.
T}:4:100:T{
A few issues came up but there are no major unresolved issues.  Rick has found
a way of keeping pad VDD from getting above 6 volts.
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Layout the SRAM array and simulate the critical signals.
T}:6:100:T{
The new layout works very well.  I need to get together with Leith to decide
how and when we want to get my changes made to the master layout.
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.SP 1
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Continue to work with the vendors on the SRAM spec and continue to push
for 25 ns 2K x 8 parts.
T}:2:100:T{
We met with Lattice to talk about the way they do business.  They are still
considered a higher risk than the other vendors.  I looked at some screened
35 ns parts from Cypress.  There were no problems with the spec changes.
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Address memory board issues.  Get better resolution on if the MID_BUS buffers
have to change to SOIC's and evaluate the impact.
T}:2:100:T{
I got new foot prints for the SOIC's.  I also started working on the 8 Mbyte
board.  There is a good chance that we will be able to get 1 Mbit chips about
the same time as we get MC-F's.
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Decide what further changes need to be made to the PDH and make these.
This includes the battery, the PAL's, and the power down protection
circuits.  (This may not get done this month.)
T}:3:50:T{
I changed the PAL equations and made some changes to make the MID_BUS timing
work.  I have listed and prioritized the PDH issues.
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DEVIATIONS, ACTION
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KEY DECISIONS
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CONCERNS, CRITICAL ELEMENTS
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SUMMARY
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