.pl 72v
.MT 4 1
.nr Ls 0
.po 0
.DS
.DE
.SP 5
.TS
tab(:);
cw(4.3i) cw(3.7i) cw(5.0i).
.B
Project Manager - Howell Felsenthal:FIREFOX:date May 86
.SP 1
Engineer - Rob Horning ::Project 7910
.R
.TE
.SP 2
.in .1i
.TS
tab(:);
c c c c
lw(4.2i) lw(.3i) nw(.3i) lw(4.1i).
.B
OBJECTIVES:MD :%:RESULTS, STATUS
.R
.SP 1
T{
Characterize the SRAM arrays.  Help with any changes required to the PC board
to improve the arrays (if needed).
T}:3:100:T{
The arrays looked fairly good except for the high capacitance on the Toshiba
corner address pins.  We plan to mix the address lines some to make the worse
case line better.  Toshiba is working on the problem.
T}
.SP 1
T{
Finish the Math board evaluation and test the changes.
T}:3:100:T{
I made all the design changes and tested them.  I also have started the ERS and
the theory of operation.
T}
.SP 1
T{
Take the Math board through PC layout.  Update the schematic.
T}:4:100:T{
The board is being built.  There are no design rule violations.  I also updated
the schematic to do parts list checks.
T}
.SP 1
T{
Turn on the 2 Mbyte RAM board with the MC-F if it arrives.
T}:4: - :T{
It did not arrive.
T}
.SP 1
T{
Continue to work with the SRAM vendors.
T}:1:100:T{
I have spent a lot of time meeting with SRAM vendors.  We still do not have any
real parts from Cypress or Toshiba.  There are a couple more small companies
that are planning to make the parts.
T}
.SP 1
T{
Help with the build of 2 Mbyte RAM boards.
T}:1:100:T{
I have 10 more 2 Mbyte RAM boards.  I do not plan to turn them on until we
have MC-F.
T}
.SP 1
T{
Continue to help with turn on.  Turn on the 1.2 CA chip when it comes.
T}:3:100:T{
We tested the AP card and everything worked.  The CA chip did not come.
T}
.SP 1
T{
vacation
T}:2::T{
T}
.TE
.in 10.1i
.sp |12v
.TS
tab(:);
cw(2.8i)
l
c
l
c
l
c
l.
.B
DEVIATIONS, ACTION
.R
.sp |15v
T{
T}
.sp |28v
.B
KEY DECISIONS
.R
.sp |30v
T{
T}
.sp |36v
.B
CONCERNS, CRITICAL ELEMENTS
.R
.sp |38v
T{
T}
.sp |49
.B
SUMMARY
.R
.sp |51
T{
T}

