.pl 72v
.MT 4 1
.nr Ls 0
.po 0
.DS
.DE
.SP 5
.TS
tab(:);
cw(4.3i) cw(3.7i) cw(5.0i).
.B
Project Manager - Tom Meyer:FIREFOX:date September 86
.SP 1
Engineer - Rob Horning ::Project 7910
.R
.TE
.SP 2
.in .1i
.TS
tab(:);
c c c c
lw(4.2i) lw(.3i) nw(.3i) lw(4.1i).
.B
OBJECTIVES:MD :%:RESULTS, STATUS
.R
.SP 1
T{
Finish evaluation of the math board.  Mainly check out the isolation circuits.
T}:1:100:T{
No problems were found with the isolation circuits.
T}
.SP 1
T{
Take the math board through PC layout.  Get it ready and run the DRC on the new
layout.
T}:3:100:T{
I ended up making several design rule changes that should make the board easier
to manufacture and more reliable.  There is better solder mask coverage on
traces going between pins of IC's and PGA's.  The inner layer pads were made
larger.  The board has been released.
T}
.SP 1
T{
Continue to help with the memory boards.
T}:2:100:T{
I helped Jim run the design rule checker program and to evaluate the errors.
I have continued to keep in touch with the RAM vendors to make sure that we
get parts.
T}
.SP 1
T{
Continue to work on getting 25 ns 2K x 8 SRAM's.
T}:2:100:T{
We have seen a few engineering sample of real 25 ns parts from Hitachi.  We
hope to see full spec parts from Cypress, Hitachi, and Toshiba in November.
T}
.SP 1
T{
Work on ultra-fox.
T}:9:70:T{
I have been spending more time on ultra-fox.  We are getting a lot of inputs
on what it should be.  I have looked into floating point and am starting to
understand what a server needs to be.  I have started to look into ways of
configuring the busses.
T}
.SP 1
T{
Help with MC-F issues.
T}:1:100:T{
The main issue that came up was that the MID_BUS buffer control timing was
not done the way that I had been told.  We did come up with a solution to this
problem.  Some architecture issues also came up and were resolved.  I spent
two or three days working on MC-F problems.
T}
.SP 1
T{
Work on math board documentation.
T}:3:100:T{
I spent more time that I had planned in this area but I also got more done than
I had planned to.  I finished the ERS and am at least half done with the theory
of operation.
T}
.SP 1
T{
T}:::T{
T}
.SP 1
T{
T}:::T{
T}
.SP 1
T{
T}:::T{
T}
.SP 1
T{
T}:::T{
T}
.SP 1
T{
T}:::T{
T}
.TE
.in 10.1i
.sp |12v
.TS
tab(:);
cw(2.8i)
l
c
l
c
l
c
l.
.B
DEVIATIONS, ACTION
.R
.sp |15v
T{
T}
.sp |28v
.B
KEY DECISIONS
.R
.sp |30v
T{
T}
.sp |36v
.B
CONCERNS, CRITICAL ELEMENTS
.R
.sp |38v
T{
T}
.sp |49
.B
SUMMARY
.R
.sp |51
T{
T}

