.pl 72v
.MT 4 1
.nr Ls 0
.po 0
.DS
.DE
.SP 5
.TS
tab(:);
cw(4.3i) cw(3.7i) cw(5.0i).
.B
Project Manager - Howell Felsenthal:Gumby?:date
.SP 1
Engineer - Rob Horning ::Project PCX1
.R
.TE
.SP 2
.in .1i
.TS
tab(:);
c c c c
lw(4.2i) lw(.3i) nw(.3i) lw(4.1i).
.B
OBJECTIVES:MD :%:RESULTS, STATUS
.R
.SP 1
T{
Finish clock specification.  Have high confidance that the worse case delay
spec is met.  Run simulations to verify that the skew goals are reasonable.
T}:10:100:T{
This took almost all my time but I got more done than I expected.  I am pretty
much done with the clock simulations.  I wrote up a summary of the clock specs
and went over my simulations with the other MTS's working on the clock.
T}
.SP 1
T{
Establish how to model and specify cross talk and run first pass simulations.
T}:3: - :T{
I did not get to this.  I got my cross talk bread board layed out and back.
T}
.SP 1
T{
Review simulation results from SRAM driver and establish what needs to be
done to come up with a spec.
T}:2: - :T{
I did not get to this.  I did talk to Jim Couts about running some tests on
the SRAM's.  I have not seen the results yet.
T}
.SP 1
T{
Continue to consult on pinouts and Gumby? layout.
T}:1:100:T{
I worked on the layout a little to gain more confidance on how long the clock
traces would be.  I also talked to the chip designers about where to put the
clocks on the pinout.
T}
.SP 1
T{
If time permits document the PC board models.
T}::20:T{
I started to do this.
T}
.SP 1
T{
Vacation
T}:6::T{
T}
.SP 1
T{
T}:::T{
T}
.SP 1
T{
T}:::T{
T}
.SP 1
T{
T}:::T{
T}
.SP 1
T{
T}:::T{
T}
.SP 1
T{
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T}
.SP 1
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.TE
.in 10.1i
.sp |12v
.TS
tab(:);
cw(2.8i)
l
c
l
c
l
c
l.
.B
DEVIATIONS, ACTION
.R
.sp |15v
T{
T}
.sp |28v
.B
KEY DECISIONS
.R
.sp |30v
T{
T}
.sp |36v
.B
CONCERNS, CRITICAL ELEMENTS
.R
.sp |38v
T{
T}
.sp |49
.B
SUMMARY
.R
.sp |51
T{
T}

