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Project Manager - Ron Rogers:Alexa:date February 87
.SP 1
Engineer - Rob Horning ::Project 7910
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.TE
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OBJECTIVES:MD :%:RESULTS, STATUS
.R
.SP 1
T{
Understand and document parity board design.  Document the DIO
and DTACK interface.
T}:3:100:T{
I understand all the details of the DIO interface and I documented how the
DTACK works.
T}
.SP 1
T{
Help with Alexa design.  Design the DIO interface and the error handling
state machine.
T}:5:80:T{
The DIO interface is done for the most part.  We figured out that the error
handling state machine is really part of the arbiter.  Russ has primary
responsibility for the arbiter.  I have helped Russ a little bit on the
arbiter.
T}
.SP 1
T{
Help with the Alexa Schematic.
T}:3:100:T{
I have most of the DIO interface, the test circuits, and the address decode
captured.
T}
.SP 1
T{
Help with any bread boarding that we decide to do.
T}:3: - :T{
We are not going to bread board.
T}
.SP 1
T{
Look into the test strategy and the diagnostic features.
T}:3:80:T{
I proposed a set of test features and have already designed them in.  I am
still waiting for more feedback on the proposal.  I did some estimating
on the amount of soft error rate testing that needs to be done.  I have
done nothing on system test.
T}
.SP 1
T{
Work on Firefox problems that come up.
T}:3:100:T{
I spent more like 4 or 5 days on Firefox issues.  There are some problems with
the RTC calibration constants.  There have been memory board questions resolved.
I have been keeping up on SRAM availability.
T}
.SP 1
T{
T}:::T{
T}
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DEVIATIONS, ACTION
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.sp |15v
T{
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KEY DECISIONS
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CONCERNS, CRITICAL ELEMENTS
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.sp |49
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SUMMARY
.R
.sp |51
T{
T}

