.pl 72v
.MT 4 1
.nr Ls 0
.po 0
.DS
.DE
.SP 5
.TS
tab(:);
cw(4.3i) cw(3.7i) cw(5.0i).
.B
Project Manager - Howell Felsenthal:Gumby?:date March 88
.SP 1
Engineer - Rob Horning ::Project PCX1
.R
.TE
.SP 2
.in .1i
.TS
tab(:);
c c c c
lw(4.2i) lw(.3i) nw(.3i) lw(4.1i).
.B
OBJECTIVES:MD :%:RESULTS, STATUS
.R
.SP 1
T{
Help with After burner issues.  Check the diode model to make sure that it is
not too aggressive.
T}:3::T{
T}
.SP 1
T{
Do the PC layout for the After burner chips to make sure that the new pinouts
do not cause too many problems.
T}:4::T{
T}
.SP 1
T{
Update the ERS and document what I have been working on so that I can free
myself up by the end of the month.
T}:8::T{
T}
.SP 1
T{
Do the schematic for the data cache array.
T}:3::T{
T}
.SP 1
T{
Continue to work on SRAM issues.  Look at the new Hitachi spice model.
T}:3::T{
T}
.SP 1
T{
Vacation
T}:3::T{
T}
.SP 1
T{
T}:::T{
T}
.SP 1
T{
T}:::T{
T}
.SP 1
T{
T}:::T{
T}
.SP 1
T{
T}:::T{
T}
.SP 1
T{
T}:::T{
T}
.SP 1
T{
T}:::T{
T}
.TE
.in 10.1i
.sp |12v
.TS
tab(:);
cw(2.8i)
l
c
l
c
l
c
l.
.B
DEVIATIONS, ACTION
.R
.sp |15v
T{
T}
.sp |28v
.B
KEY DECISIONS
.R
.sp |30v
T{
T}
.sp |36v
.B
CONCERNS, CRITICAL ELEMENTS
.R
.sp |38v
T{
T}
.sp |49
.B
SUMMARY
.R
.sp |51
T{
T}

