.DF
                                                             4/14/88
                                                         Rob Horning

.DE

This is a summary of the PC layout work that I did for the After burner chips
to determine the effects of having a non-optimized pinout.  The following
assumptions were made:

.AL
.LI
The data cache is harder to hook up and more critical than the instruction
cache and so only the data cache was laid out.
.LI
Both the data and tag portions use 64K x 4 SRAM's.
.LI
Address signals and control signals have the same timing requirements and
loading (per input).
.LI
True-compliment drivers may be used.  The pinout used was not true compliment,
but control lines used only one output.
.LI
Control signals should not share an Afterburner package with more than three
heavily loaded buffers that drive address lines. (The address lines that drive
only the tags are not heavily loaded.)
.LI
It is only a small want to distribute the loading evenly on the After burners.
Cooling is not a big problem.
.LI
There are two output pairs on three sides of the chip.  Each pair is separated
by VCC and has ground on the outside.
.LI
The six inputs all come into the fourth side and are separated by powers and
grounds.
.LI
There  will be 12 by-pass capacitors for each After burner.  One for each VCC
(6), one for each VCC2 (4), and two for VDL.
.LE

The pinout assumed is shown below:

.DS

              o   o       o   o
              u   u       u   u
            g t v t g v g t v t g
            n b d a n d n b d a n
            d 4 d 4 d d d 3 d 3 d
            | | | | | | | | | | |
     gnd -                        - gnd
   outa5 -                        - out2b
     vdd -                        - vdd
   outb5 -                        - out2a
     gnd -                        - gnd
     vdd -                        - vdd
     gnd -                        - gnd
   outa6 -                        - out1b
     vdd -                        - vdd
   outb6 -                        - out1a
     gnd -                        - gnd
            | | | | | | | | | | |
            i v i v i v i v i v i
            n d n d n d n d n d n
            6 l 5 l 4 d 3 l 2 l 1

.DE

The above pinout is very difficult to hook up.  It was all hooked up but at a
cost.  The lines that connect to the array are longer and the impedance is
less controlled.

The following model should be used for the worse case address driver

.DS
              33-60 Ohms   -SRAM1 . . . SRAM4-
                350 pS    |                    |
                -----------SRAM1 . . . . SRAM4-------DIODES
               |
  40-86 Ohms  | 33-60 Ohms  40-86 Ohms           40-86 Ohms
    150 pS   |  400 pS       90 pS                175 pS
BJT---------O---------SRAM1-------SRAM2 . . . SRAM5-----DIODES
             |      |                               |
              |       -SRAM1------SRAM2 . . . SRAM5-
               |
                | 33-60 Ohms
                 | 250 pS
                  --------SRAM1 . . . . SRAM5-------DIODES
                         |                     |
                          -SRAM1 . . . . SRAM5-

.DE
Note the following changes to the model:

.AL
.LI
There is a short fairly high impedance line from the BJT before the signal
branches out.  This impedance could be lowered some if this would help.
.LI
The distance between the SRAM's has been increased to 90 pS.
.LI
The distance from the last SRAM in each row to the diodes has been increased
to 175 pS.
.LI
Each of the three row pairs have there own set of diodes.
.LI
One of the row pairs has only 5 SRAM's each.
.LE

The above line  is the worse case slow line.  The fastest line drives as few as
8 SRAM's.  This may require us to put extra delay in the line going into the
After burner.

There are six different ways in which the After burner outputs may be connected
to the data cache array.

.AL
.LI
General address lines -  These connect to all the SRAM's. (56 SRAM's)
.LI
Data only address lines -  These connect to all data SRAM's. (40 SRAM's)
.LI
Tag only address lines - These connect to all TAG SRAM's. (16 SRAM's)
.LI
Write control for data - This line connects to all data SRAM's. (40 SRAM's)
.LI
Write control for tag - This line connects to all tag SRAM's. (16 SRAM's)
.LI
Chip enable - There are two lines and each connects to half the data SRAM's
and half the tag SRAM's. (28 SRAM's)
.LE

The number of SRAM's in the above list assumes that the SRAM's are four bits
wide.  The control lines are different than address lines because they switch
at different times and they also can only use half of a true-compliment buffer.
If true-complement buffers are assumed than two buffers will be needed for the
write control for data line.

There will always be two write lines and two chip enable lines regardless of
the SRAM option, but the number of address lines will change depending on the
option.  The table below shows the number of address signals needed for three
different SRAM configurations:

.DS
.TB "Number of Address Lines"
.TS
center tab (/) box;
l|c|c|c|c.
Data size/16K x 4/32K x 8/64K x 4/256K x4
Tag size/16K x 4/16K x 4/64K x 4/256K x4
_
General/12/14/14/16
Data only/2/1/2/2
Tag only/2/1/2/2
_
Total/16/16/18/20
.TE
.DE

Note that up to 256K x 4 SRAM's can be supported with four After burners
assuming that there are four control lines.  If true-complement drivers are
used then the write control line for the data SRAM's requires two buffers and
so we would be one buffer short.  It is likely that we would ground one of
the tag only address lines in this case rather than add a fifth After burner.

The table below shows how each of the four After burners are used in the
current layout.  This layout assumes 64K x 4 SRAM's for the data and tag.

.DS
.TB "After Burner Use"
.TS
center tab (/) box;
l|c|c|c|c.
After Burner/1/2/3/4
_
General Address/4/4/3/3
Data only Address/1/1/ / 
Tag only Address/1/1/ / 
Chip Enable/ / /1/1
Write Data/ / /1/1
Write Tag/ / /1/ 
Not Used/ / / /1
.TE
.DE

All signals going into and out of the After burners are referenced to ground or
power supplies.  In general most ground noise will couple into the signals and
supplies and will not be seen.  There will be a problem when the power planes
move relative to the ground planes because, some of the signals use the power
planes as AC grounds.  To prevent the After burners from causing power plane
noise, the supply pins will be some what isolated from the power planes.  The
by-pass capacitors will be connected with a very short trace to the After
burner and ground.  The After burners and the by-pass capacitors will share
vias.  The vias will not be connected directly to the power planes.  A trace
will be used to connect the via to the power plane.  The length and width of
this trace will be determined later.  At this time the After burner is not
depending on the power plane for by-passing.

